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MITSUBISHI LSIs
M5M5V2132GP-5H,-5,-6,-7,-8
2097152-BIT(65536-WORD BY 32-BIT) SYNCHRONOUS BURST SRAM
When CLK is stopped and all inputs (Address, Burst control,
CLK etc. ) are fixed in CMOS level, the SRAM becomes in the
power-down state that is called "CLK stopped stand-by mode".
During CLK stopped stand-by mode, power supply current is
almost same as snooze mode even if the SRAM is selected.
When CLK is active again, the SRAM immediately recovers from
CLK stopped stand-by mode to normal operation mode.
The burst mode control (MODE), and the flow-through enable
(FT) are DC operated pins. MODE pin will allow the choice of
either an interleaved burst, or a linear burst. FT pin normally is
V
DD
. When FT is pulled Vss, the SRAM changes non-pipelined
type with flow-through output. FT input fixed to Vss is only used
for a test mode.
The burst operation is initiated by either address status
processor (ADSP) or address status controller (ADSC). The burst
advance pin (ADV) controls subsequent burst addresses.
e.
to chang
DESCRIPTION
The M5M5V2132 is a family of 2M bit synchronous SRAMs
organized as 65536-words of 32-bit. The M5M5V2132 provides a
high speed secondary cache solution for microprocessors. The
design integrates a 2-bit burst counter, input and output registers
with the ultra fast 2M bit SRAM on a single monolithic circuit. This
design reduces component count of cache data RAM solutions.
Mitsubishi's SRAMs are fabricated with high-performance, low
power Super CMOS technology, providing greater reliability. This
device operates on 3.3V power / 2.5V I/O supply or a single 3.3V
power supply , and are directly LVTTL compatible.
FEATURES
Access times / Cycle times
......................
M5M5V2132GP-5H
......................
M5M5V2132GP-5
.....................
M5M5V2132GP-6
.....................
M5M5V2132GP-7
.....................
M5M5V2132GP-8
5.0ns/7.5ns (133MHz)
5.0ns/8.5ns (117MHz)
5.5ns/10.0ns(100MHz)
7.0ns/13.3ns (75MHz)
8.0ns/15.0ns (66MHz)
...........................
875mW (typ)
Low power dissipation
...........................
3.3mW (typ)
Active(133MHz)
Stand-by
-5H,-5,-6 ....... 3.3V(3.13V ~ 3.47V )power
/ 2.5V(2.37V ~ 2.90V) I/O supply
or Single 3.3V(3.13V ~ 3.47V )power supply
....... 3.3V(3.13V ~ 3.60V )power
-7 ,-8
/ 2.5V(2.37V ~ 2.90V) I/O supply
or Single 3.3V(3.13V ~ 3.60V )power supp
Package
100pin TQFP
2
Body Size (14.0 x 20.0 mm ) Pin Pitch (0.65 mm)
Fully registered inputs and outputs (Pipeline operation)
Global write control or individual byte write control
MODE pin allows either liner or interleaved burst
Snooze mode pin (ZZ) for power down
CLK stopped stand-by mode
32-bit wide data I/O
APPLICATION
Pentium
TM
/ PowerPC
caches
TM
and High-end processor second level
FUNCTION
Synchronous circuitry allows for precise cycle control triggered by
a positive edge clock transition. Synchronous signals include : all
addresses, all data inputs, all chip selects (S
1
, S
2
, S
2
), burst
control inputs (ADSC, ADSP, ADV) and write enables (MBW, GW,
BW
1
, BW
2
, BW
3
, BW
4
). S
2
and S
2
provide easy depth expansion.
The write operation can be performed by two methods. The
global write enable (GW) will perform a write to all 32 bits. Byte
wide writes are controlled by the master byte write enable (MBW)
and the 4 individual byte write enables (BW
1-
BW
4
). The byte write
cycle will write from one to four bytes. The write cycle is internally
self-timed, eliminating the complex signal generation of an off chip
write.
Asynchronous signals are output enable (OE), snooze mode pin
(ZZ) and clock (CLK). The HIGH input of ZZ pin puts the SRAM in
the power-down state. When ZZ is pulled to LOW, the SRAM
normally operates after 30ns of the wake up period.
1
2
ENABLE
A
8
ADDRESS ADVANCE
INPUT
ADV
BURST
ADSP
CONTROL
INPUTS
ADSC
OUTPUT ENABLE
INPUT
OE
MASTER BYTE
MBW
WRITE ENABLE
GLOBAL WRITE
GW
CLOCK INPUT
CLK
89
V
DD
CHIP SELECT
INPUT
S
2
BW
1
BYTE
BW
2
WRITE
ENABLES
BW
3
BW
4
S
2
CHIP SELECT
INPUTS
S
1
ADDRESS
A
9 81
INPUTS
PIN CONFIGURATION (TOP VIEW)
ADDRESS
INPUTS
(0V)V
SS 90
98
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
97
96
95
94
93
92
91
88
87
86
85
84
83
82
A
7 99
A
6
100
NC
1
DATA
DQ
17 2
INPUTS/
OUTPUTS
DQ
18 3
V
DD
Q
4
(0V)V
SS
Q
5
DQ
19 6
DATA
DQ
20 7
INPUTS/
8
OUTPUTS
DQ
21
DQ
22 9
(0V)V
SS
Q
10
V
DD
Q
11
DATA
DQ
23 12
INPUTS/
OUTPUTS
DQ
24 13
14
15
2097152-BIT(65536-WORD BY 32-BIT) SYNCHRONOUS BURST SRAM
Outline :100P6A-A(LQFP)
M5M5V2132GP
FLOW-
THROUGH
ENABLE
FT
V
DD
NC
DQ
16 DATA
INPUTS/
DQ
15 OUTPUTS
V
DD
Q
V
SS
Q(0V)
DQ
14
DQ
13 DATA
INPUTS/
DQ
12 OUTPUTS
DQ
11
V
SS
Q(0V)
V
DD
Q
DQ
10 DATA
INPUTS/
DQ
9 OUTPUTS
V
SS
(0V)
NC
V
DD
SNOOZE
MODE
ZZ
INPUT
DQ
8 DATA
INPUTS/
DQ
7 OUTPUTS
V
DD
Q
V
SS
Q(0V)
DQ
6
DQ
5 DATA
INPUTS/
DQ
4 OUTPUTS
DQ
3
V
SS
Q(0V)
V
DD
Q
DQ
2 DATA
DQ
1
NC
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
31
INPUTS/
OUTPUTS
NC
16
(0V)V
SS 17
DATA
DQ
25 18
INPUTS/
OUTPUTS
DQ
26 19
V
DD
Q
20
(0V)V
SS
Q
21
DQ
27 22
DATA
DQ
28 23
INPUTS/
OUTPUTS
DQ
29 24
DQ
30 25
(0V)V
SS
Q
26
V
DD
Q
27
DATA
DQ
31 28
INPUTS/
OUTPUTS
DQ
32 29
NC
30
MITSUBISHI LSIs
M5M5V2132GP-5H,-5,-6,-7,-8
V
CC
Q
: 2.5V or 3.3V , NC : NO CONNECTION
NC
A
15
A
10
A
11
A
12
ADDRESS
INPUTS
A
13
A
14
NC
NC
V
DD
V
SS
(0V)
NC
NC
A
0
A
1
A
2
ADDRESS
A
3
INPUTS
A
4
A
5
BURST
MODE
MODE
CONTROL
MITSUBISHI LSIs
M5M5V2132GP-5H,-5,-6,-7,-8
2097152-BIT(65536-WORD BY 32-BIT) SYNCHRONOUS BURST SRAM
BLOCK DIAGRAM
V
DD
(3.3V)
15 41 65 91
V
SS
(0V)
17 40 67 90
V
DD
Q (2.5V or 3.3V)
4 11 20 27 54 61 70 77
V
SS
Q (0V)
5 10 21 26 55 60 71 76
ADDRESS
INPUTS
A
0 37
A
1 36
A
2 35
A
3 34
A
4 33
A
5 32
A
6 100
A
7 99
A
8 82
A
9 81
A
15 49
A
10 48
A
11 47
A
12 46
A
13 45
A
14 44
31
64
83
89
ADDRESS
REGISTER
16
14
16
A
0
A
1
Linear/Interleaved
BURST
COUNTER
BURST
CONTROL
INPUTS
ADSC
85
ADSP
84
BW
1
LOAD
Q
0
A
0'
D
1
~D
8
BYTE 1
WRITE REGISTER
BYTE 1
WRITE DRIVER
8
93
D
9
~D
16
BW
2
BYTE
WRITE
ENABLES
94
BYTE 2
WRITE REGISTER
BYTE 2
WRITE DRIVER
8
D
17
~D
24
BW
3
95
BYTE 3
WRITE REGISTER
BYTE 3
WRITE DRIVER
8
64K x 32
MEMORY
ARRAY
32
D
25
~D
32
MASTER
BW
4
BYTE
WRITE
MBW
ENABLE
GLOBAL
GW
WRITE
ENABLE
S
1
CHIP SELECT
INPUTS
OUTPUT
BUFFERS
Q
1
A
1'
OUTPUT
REGISTERS
D
0
D
1
96
87
88
98
97
92
BYTE 4
WRITE REGISTER
BYTE 4
WRITE DRIVER
8
32
S
2
S
2
CHIP
SELECT
REGISTER
32
INPUT
REGISTERS
CHIP
SELECT
DELAY
REGISTER
OUTPUT
ENABLE
INPUT
FLOW-
THROUGH
ENABLE
OE
FT
4
86
14
Note: The Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and
timing diagrams for detailed information.
3
DATA INPUTS/OUTPUTS
BURST
MODE
CONTROL
MODE
SNOOZE MODE
INPUT
ZZ
ADDRESS
ADVANCE
ADV
INPUT
CLOCK
CLK
INPUT
52
53
56
57
58
59
62
63
68
69
72
73
74
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
75
DQ
14
78
DQ
15
79
DQ
16
2
DQ
17
3
DQ
18
6
DQ
19
7
DQ
20
8
DQ
21
9
DQ
22
12
DQ
23
13
DQ
24
18
DQ
25
19
DQ
26
22
DQ
27
23
DQ
28
24
DQ
29
25
DQ
30
28
DQ
31
29
DQ
32
MITSUBISHI LSIs
M5M5V2132GP-5H,-5,-6,-7,-8
2097152-BIT(65536-WORD BY 32-BIT) SYNCHRONOUS BURST SRAM
PIN FUNCTIONS
Pin
A0~A15
MBW
Name
Synchronous
Address Inputs
Synchronous Master
Byte Write Enables
Synchronous Global
Write Enables
Synchronous Byte
Write Enables
Function
These inputs are registered and must meet the setup and hold times around
the rising edge of CLK.
This active LOW input is used to enable the individual byte write operation. The
individual byte write operation is performed when MBW is LOW and GW is HIGH. The
global write operation (a write to all 32 bits) is performed when GW is LOW.
This active LOW input is used to enable the global write operation (a write to all 32 bits)
and must meet the setup and hold times around the rising edge of CLK.
These active LOW inputs allow individual bytes to be written and must meet the setup
and hold times around the rising edge of CLK. A byte write enables is LOW for a
WRITE cycle and HIGH for a READ cycle. BW1 controls DQ1~DQ8. BW2 controls
DQ9~DQ16. BW3 controls DQ17~DQ24. BW4 controls DQ25~DQ32. Data I/O are
tristated if any of these four inputs are LOW.
This signal latches the address, data, chip enables, byte write enables and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold
times around the clock's rising edge.
This active LOW input is used to enable the device and conditions internal use of
ADSP. This input is sampled only when a new external address is loaded.
This active LOW input is used to enable the device. This input is sampled only when a
new external address is loaded. This input can be used for memory depth expansion.
This active HIGH input is used to enable the device. This input is sampled only when a
new external address is loaded. This input can be used for memory depth expansion.
This active LOW asynchronous input enables the data I/O output drivers.
Byte 1 is DQ1~DQ8; Byte 2 is DQ9~DQ16; Byte 3 is DQ17~DQ24; Byte 4 is DQ25~DQ32.
Input data must meet setup and hold times around the rising edge of CLK.
This asynchronous input allows the selection either normal operation mode or snooze
mode that the SRAM is in the power-down state even if CLK is operated. This active
HIGH asynchronous input puts the SRAM in the snooze mode. At this time, the data I/O
output drivers are disabled and input leak current flows to this pin. When this pin is
LOW or NC, the SRAM normally operates.
This DC operated pin allows the choice of either an interleaved burst or a linear burst.
If this pin is VDD or NC, an interleaved burst occurs. When this pin is Vss, a linear
burst occurs, and input leak current flows to this pin.
This DC operated pin is used as a test mode pin. Normally, this pin is VDD or NC.
When this pin is Vss, the SRAM changes non-pipelined type with flow-through output,
and input leak current flows to this pin.
This active LOW input interrupts any ongoing burst, causing a new external address to
be latched. A READ is performed using the new address, independent of the byte write
enables and ADSC but dependent upon S2 and S2. ADSP is ignored if S1 is HIGH.
Power-down state is entered if S2 is LOW or S2 is HIGH.
This active LOW input interrupts any ongoing burst and causes a new external address
to be latched. A READ or WRITE is performed using the new address if all chip enables
are active. Power-down state is entered if one or more chip enables are inactive.
This active LOW input is used to advance the internal burst counter, controlling burst
access after the external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). This pin must be HIGH at the rising edge
of the first clock after an ADSP cycle is initiated if a WRITE cycle is desired (to ensure
use of correct address)
Power Supply (3.3V)
Ground (0V)
I/O Buffer Supply (2.5V or 3.3V)
I/O Buffer Ground (0V)
GW
BW1, BW2,
BW3, BW4
CLK
Clock Input
S1
S2
S2
OE
DQ1~DQ32
ZZ
Synchronous
Chip Select Input
Synchronous
Chip Select Input
Synchronous
Chip Select Input
Output Enable Input
Data I/O
Snooze Mode Input
MODE
Burst Mode Control
FT
Flow-through Enable
ADSP
Synchronous
Address Status Processor
ADSC
Synchronous
Address Status Controller
Synchronous
Address Advance
ADV
VDD
VSS
VDDQ
VSSQ
VDD
VSS
VDDQ
VSSQ
4
MITSUBISHI LSIs
M5M5V2132GP-5H,-5,-6,-7,-8
2097152-BIT(65536-WORD BY 32-BIT) SYNCHRONOUS BURST SRAM
DC OPERATED TRUTH TABLE
Name
MODE
FT
Input status
VDD or NC
Vss
VDD or NC
Vss
Operation
Interleaved Burst Sequence
Linear Burst Sequence
Pipelined SRAM
Non-pipelined SRAM (Test mode)
Note 1. MODE and FT are DC operated pins.
2. NC means No-Connection.
3. Normally, FT is pulled to Vcc or NC. FT input fixed to Vss is only used for a test mode.
4. See BURST SEQUENCE TABLE about Interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
Interleaved Burst Sequence
(when MODE = VDD or NC)
Operation
First access, latch external address
Second access (first burst address)
Third access (second burst address)
Fourth access (third burst address)
A
15
-A
2
A
15
-A
2
latched A
15
-A
2
latched A
15
-A
2
latched A
15
-A
2
A
1
A
1
latched A
1
latched A
1
latched A
1
A
0
A
0
latched A
0
latched A
0
latched A
0
Linear Burst Sequence (when MODE = Vss)
Operation
First access, latch external address
Second access (first burst address)
Third access (second burst address)
Fourth access (third burst address)
A
15
-A
2
A
15
-A
2
latched A
15
-A
2
latched A
15
-A
2
latched A
15
-A
2
A
1
, A
0
0, 0
0, 1
1, 0
1, 1
0, 1
1, 0
1, 1
0, 0
1, 0
1, 1
0, 0
0, 1
1, 1
0, 0
0, 1
1, 0
Note 5. The burst sequence wraps around to its initial state upon completion.
SYNCHRONOUS TRUTH TABLE
S1
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
S2
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
S2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
ADSP
X
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
ADSC
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
Write
X
X
X
X
X
X
L
H
H
H
L
L
H
H
L
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Address
used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Operation
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Note 6. X means "don't care". H means logic HIGH. L means logic LOW.
7. Write =L means "WRITE" operation in WRITE TRUTH TABLE.
Write =H means "READ" operation in WRITE TRUTH TABLE.
8. All inputs in this table must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
9. ADSP LOW always initiates an internal READ at the L-H edge of CLK.
10. Operation finally depends on status of asynchronous input pins (ZZ and OE).
See ASYNCHRONOUS TRUTH TABLE.
5
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