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MPSA75

Description
300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN
CategoryDiscrete semiconductor    The transistor   
File Size519KB,4 Pages
ManufacturerCentral Semiconductor
Download Datasheet Parametric Compare View All

MPSA75 Overview

300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN

MPSA75 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerCentral Semiconductor
Parts packaging codeTO-92
package instructionTO-92, 3 PIN
Contacts3
Reach Compliance Code_compli
Maximum collector current (IC)0.5 A
ConfigurationDARLINGTON
Minimum DC current gain (hFE)10000
JEDEC-95 codeTO-92
JESD-30 codeO-PBCY-T3
JESD-609 codee0
Number of components1
Number of terminals3
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeROUND
Package formCYLINDRICAL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typePNP
Certification statusNot Qualified
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
Transistor component materialsSILICON
Nominal transition frequency (fT)125 MHz
MPSA92
MPSA93
w w w. c e n t r a l s e m i . c o m
SILICON
HIGH VOLTAGE
PNP TRANSISTORS
DESCRIPTION:
The CENTRAL SEMICONDUCTOR MPSA92 and
MPSA93 are silicon PNP transistors designed for
high voltage applications.
MARKING: FULL PART NUMBER
TO-92 CASE
MAXIMUM RATINGS:
(TA=25°C unless otherwise noted)
SYMBOL
Collector-Base Voltage
VCBO
Collector-Emitter Voltage
VCEO
Emitter-Base Voltage
Continuous Collector Current
Power Dissipation
Power Dissipation (TC=25°C)
Operating and Storage Junction Temperature
Thermal Resistance
Thermal Resistance
ELECTRICAL
SYMBOL
ICBO
ICEO
IEBO
BVCBO
BVCEO
BVEBO
VCE(SAT)
VBE(SAT)
hFE
hFE
hFE
fT
Cob
CHARACTERISTICS:
(TA=25°C)
TEST CONDITIONS
VCB=200V
VCE=160V
VEB=3.0V
IC=100μA
IC=1.0mA
IE=100μA
IC=20mA, IB=2.0mA
IC=20mA, IB=2.0mA
VCE=10V, IC=1.0mA
VCE=10V, IC=10mA
VCE=10V,
VCE=20V,
IC=30mA
IC=10mA, f=100MHz
VCB=20V, IE=0, f=1.0MHz
VEBO
IC
PD
PD
TJ, Tstg
JA
JC
MPSA92
MIN
MAX
-
250
-
-
300
300
5.0
-
-
25
40
25
50
-
-
100
-
-
-
0.5
0.9
-
-
-
-
6.0
MPSA92
300
300
5.0
500
625
1.5
MPSA93
200
200
UNITS
V
V
V
mA
mW
W
°C
°C/W
°C/W
-65 to +150
200
83.3
MPSA93
MIN
MAX
-
-
-
-
200
200
5.0
-
-
25
40
25
50
-
250
100
-
-
-
0.4
0.9
-
-
-
-
8.0
UNITS
nA
nA
nA
V
V
V
V
V
MHz
pF
R2 (15-December 2014)

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Description 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN NPN, Si, SMALL SIGNAL TRANSISTOR, TO-92 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN RF SMALL SIGNAL TRANSISTOR 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN 300,000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN
Is it lead-free? Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead -
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible -
Maker Central Semiconductor Central Semiconductor Central Semiconductor Central Semiconductor Central Semiconductor Central Semiconductor Central Semiconductor Central Semiconductor Central Semiconductor -
Parts packaging code TO-92 TO-92 TO-92 TO-92 TO-92 TO-92 - TO-92 TO-92 -
package instruction TO-92, 3 PIN TO-92, 3 PIN CYLINDRICAL, O-PBCY-T3 TO-92, 3 PIN TO-92, 3 PIN TO-92, 3 PIN - CYLINDRICAL, O-PBCY-T3 CYLINDRICAL, O-PBCY-T3 -
Contacts 3 3 3 3 3 3 - 3 3 -
Reach Compliance Code _compli unknow not_compliant not_compliant _compli unknow unknow not_compliant _compli -
Maximum collector current (IC) 0.5 A 0.5 A 0.3 A 0.5 A 0.5 A 0.5 A - 0.15 A 0.6 A -
Configuration DARLINGTON DARLINGTON SINGLE DARLINGTON DARLINGTON DARLINGTON SINGLE SINGLE SINGLE -
Minimum DC current gain (hFE) 10000 10000 50 10000 1000 1000 60 50 40 -
JEDEC-95 code TO-92 TO-92 TO-92 TO-92 TO-92 TO-92 TO-92 TO-92 TO-92 -
JESD-30 code O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 O-PBCY-T3 -
JESD-609 code e0 e0 e0 e0 e0 e0 e0 e0 e0 -
Number of components 1 1 1 1 1 1 1 1 1 -
Number of terminals 3 3 3 3 3 3 3 3 3 -
Maximum operating temperature 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C 150 °C -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
Package shape ROUND ROUND ROUND ROUND ROUND ROUND ROUND ROUND ROUND -
Package form CYLINDRICAL CYLINDRICAL CYLINDRICAL CYLINDRICAL CYLINDRICAL CYLINDRICAL CYLINDRICAL CYLINDRICAL CYLINDRICAL -
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
Polarity/channel type PNP NPN NPN PNP NPN PNP NPN NPN PNP -
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified -
surface mount NO NO NO NO NO NO NO NO NO -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE -
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
Transistor component materials SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON -
Nominal transition frequency (fT) 125 MHz 125 MHz 20 MHz 125 MHz 100 MHz 100 MHz 650 MHz 60 MHz 60 MHz -
Maximum power dissipation(Abs) - - 0.625 W 0.625 W 1.5 W 0.625 W 0.35 W 0.625 W 0.625 W -
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