®
ISO
2
-CMOS
MT8880C/MT8880C-1
Integrated DTMF Transceiver
Features
•
•
•
•
•
•
•
Complete DTMF transmitter/receiver
Central office quality
Low power consumption
Microprocessor port
Adjustable guard time
Automatic tone burst mode
Call progress mode
ISSUE 2
May 1995
Ordering Information
MT8880CE/CE-1
20 Pin Plastic DIP
MT8880CC/CC-1
20 Pin Ceramic DIP
MT8880CS/CS-1
20 Pin SOIC
MT8880CN/CN-1
24 Pin SSOP
MT8880CP/CP-1
28 Pin Plastic LCC
-40°C to +85°C
based upon the industry standard MT8870
monolithic DTMF receiver; the transmitter utilizes a
switched capacitor D/A converter for low distortion,
high accuracy DTMF signalling. Internal counters
provide a burst mode such that tone bursts can be
transmitted with precise timing. A call progress filter
can be selected allowing a microprocessor to
analyze
call
progress
tones.
A
standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors. The
MT8880C-1 is functionally identical to the MT8880C
except for the performance of the receiver section,
which is enhanced to accept and reject lower signal
levels.
Applications
•
•
•
•
•
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8880C/C-1 is a monolithic DTMF transceiver
with call progress filter. It is fabricated in Mitel’s
ISO
2
-CMOS technology, which provides low power
dissipation and high reliability. The DTMF receiver is
TONE
∑
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
Φ2
CS
R/W
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
4-33
MT8880C/MT8880C-1
ISO
2
-CMOS
GS
NC
IN-
IN+
VDD
St/GT
EST
20 PIN CERDIP/PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20 24 28
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
1
2
4
6
7
Name
IN+ Non-inverting op-amp input.
IN-
GS
Inverting op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Description
V
Ref
Reference Voltage
output, nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig. 13).
V
SS
Ground input (0V).
8 OSC1 DTMF clock/oscillator input.
9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
R/W
Read/Write
input. Controls the direction of data transfer to and from the MPU and the
transceiver registers. TTL compatible.
CS
Φ2
Chip Select,
TTL input (CS=0 to select the chip).
System Clock
input. TTL compatible.
N.B.
Φ2
clock input need not be active when the
device is not being accessed.
RS0
Register Select
input. See register decode table. TTL compatible.
10 12 TONE
Tone
output (DTMF or single tone).
11 13
10 12 14
11 13 15
12 14 17
13 15 18 IRQ/
Interrupt Request to MPU
(open drain output). Also, when call progress (CP) mode has
CP been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.
14- 18- 19- D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or
Φ2
is low.
17 21 22
18 22 26
ESt
Early Steering
output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
19 23 27 St/GT
Steering Input/Guard Time
output (bidirectional). A voltage greater than V
TSt
detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than V
TSt
frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 28
8,9
16,
17
V
DD
Positive power supply input (+5V typical).
NC
No Connection.
3,5,
10,
11,
16,
23-
25
4-34
TONE
R/W
CS
RS0
NC
Φ2
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
RS0
4
3
2
1
28
27
26
•
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
28 PIN PLCC
ISO
2
-CMOS
Functional Description
The MT8880C/C-1 Integrated DTMF Transceiver
architecture consists of a high performance DTMF
receiver with internal gain setting amplifier and a
DTMF generator which employs a burst counter such
that precise tone bursts and pauses can be
synthesized. A call progress mode can be selected
such that frequencies within the specified passband
can be detected. A standard microprocessor
interface allows access to an internal status register,
two control registers and two data registers.
MT8880C/MT8880C-1
C1
R1
IN+
IN-
C2
R4
R5
GS
R3
R2
V
Ref
MT8880C/C-1
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
(A
V
diff) = R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2 R1
2
+ (1/ωC)
2
Input Configuration
The input arrangement of the MT8880C/C-1 provides
a differential-input operational amplifier as well as a
bias source (V
Ref
) which is used to bias the inputs at
V
DD
/2. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 4 - Differential Input Configuration
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
IN+
C
R
IN
IN-
R
F
GS
V
Ref
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
MT8880C/C-1
Figure 3 - Single-Ended Input Configuration
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Fig. 7). These filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
4-35
MT8880C/MT8880C-1
Steering Circuit
ISO
2
-CMOS
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
c
(see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
GTP
), v
c
reaches the threshold
(V
TSt
) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Figure 7)
into the Receive Data Register. At this point the GT
output is activated and drives v
c
to V
DD
. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
the
selected, the IRQ/CP pin will pull low when
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
t
REC
= t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see AC
Electrical Characteristics) and t
REC
is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times for tone
present (t
GTP
) and tone absent (t
GTA
). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.
t
GTP
= (R
P
C1) In [V
DD
/ (V
DD
-V
TSt
)]
t
GTA
= (R1C1) In (V
DD
/V
TSt
)
V
DD
C1
St/GT
R
P
= (R1R2) / (R1 + R2)
R1
ESt
R2
a) decreasing tGTP; (tGTP < tGTA)
V
DD
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)
t
GTA
= (RpC1) In (V
DD
/V
TSt
)
V
DD
St/GT
ESt
R1
C1
R
P
= (R1R2) / (R1 + R2)
Vc
V
DD
C1
St/GT
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
MT8880C/C-1
R1
ESt
R2
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
b) decreasing tGTA; (tGTP > tGTA)
Figure 5 - Basic Steering Circuit
4-36
Figure 6 - Guard Time Adjustment
ISO
2
-CMOS
Increasing t
REC
improves talk-off performance since
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t
REC
with a long t
DO
would be appropriate for
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 9 with a description of the events in Figure 11.
F
LOW
MT8880C/MT8880C-1
F
HIGH
DIGIT
D
3
D
2
D
1
D
0
697
697
697
770
770
770
852
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Call Progress Filter
A call progress mode, using the MT8880C/C-1, can
be selected allowing the detection of various tones
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
DTMF signals cannot be detected if CP mode has
been selected (see Table 5). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hard-
limited by a high gain comparator with the IRQ/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
a microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ/CP
pin will remain low.
852
852
941
941
941
697
770
852
941
0= LOGIC LOW, 1= LOGIC HIGH
Figure 7 - Functional Encode/Decode Table
LEVEL
(dBm)
DTMF Generator
The DTMF transmitter employed in the MT8880C/C-
1 is capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding format shown in Figure 7 must be written to
the transmit Data Register. Note that this is the same
as the receiver output code. The individual tones
which are generated (f
LOW
and f
HIGH
) are referred to
as Low Group and High Group tones. As seen from
the table, the low group frequencies are 697, 770,
852 and 941 Hz. The high group frequencies are
1209, 1336, 1477 and 1633 Hz. Typically, the high
group to low group amplitude ratio (pre-emphasis) is
2dB to compensate for high group attenuation on
long loops.
-25
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
0
= Reject
250
500
FREQUENCY (Hz)
750
= May Accept
AAAAAAAAAA
AAAAAAAAAA
AAAAAAAAAA
= Accept
AAAAAAAAAA
AAAAAAAAAA
Figure 8 - Call Progress Response
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
4-37
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