TC9208M datasheet, PDF - EEWORLD Datasheet

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TC9208M: Description8-Port 10/100/1000 Smart Ethernet Switch; File Size666KB，53 Pages; ManufacturerETC

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TC9208M Overview

8-Port 10/100/1000 Smart Ethernet Switch

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TC9208M

Preliminary Data Sheet

8-Port 10/100/1000 Smart Ethernet Switch

Features

Stand Alone Switch On A Chip

8 Ethernet 10/100/1000 ports

MII/GMII interface for all ports

Trunk group support

Four Classes of Service (CoS) selectable for

each port and/or checked via IP Header and

802.1Q VLAN Tag

Eight port-based VLANs

Maximum throughput, non head-of-line

blocking architecture

Embedded SSRAM packet buffer/address table

8K MAC address table

Each port is configurable to 10 full/half duplex,

100 full/half duplex and 1000 full duplex mode

Flow-control ability is able to set for both full

and half duplex mode

Broadcast throttling

Port Mirroring

Serial EEPROM Interface, EEPROM is optional

MDIO master for PHY configuration / polling

0.18 micron technology

2V and 3.3V dual voltage power supply

Packaged in PBGA 292

27 MHz crystal input only

This feature allows improved

multimedia applications.

support

for

The chip embeds IEEE 802.3 MAC functions for

each port and these functions support full and half

duplex modes for both 10 and 100 Mbits/s data

rates and full duplex for 1000 Mbit/s. Each port

includes dedicated receive and transmit FIFOs

with necessary logic to implement flow control for

both full and half duplex modes. TC9208M uses

IEEE 802.3x frame based flow control for full

duplex and backpressure for half duplex.

TC9208M handles an 8K address-lookup table

with searching, self-learning, and automatic aging,

at very high speed and excellent address space

coverage. Forwarding rules are implemented

according to IEEE 802.1D specifications. Filtering

capabilities for bad packets and packets with

Reserved Group Address DA are also provided.

Increased interconnection bandwidth can be

achieved by using TC9208M’s trunking

capabilities. Several load-balancing schemes are

provided through pin and EEPROM configuration.

A port mirror feature, which it includes bad frames

optionally, can be used for debugging network

problems.

The pin configuration interface comprises 40

configurations, which are shared with GMII output

pins by latching the configuration data during

reset. An external EEPROM device can also be

used to configure the TC9208M at power-up. With

reference to pin configuration interface, the

EEPROM extends the chip’s configuration

capability with new features and enables a

jumper-less configuration mode using a parallel

interface for reprogramming. A virtual internal

EEPROM mode is also provided to enable the

use of the programming interface in the absence

of external EEPROM. TC9208M can make

effective use by most of its features using only the

pin configuration interface.

TC9208M includes a physical layer configuration /

polling entity, which it is use to configure the phy

functions and to monitor the physical layer

transceiver’s speed, duplex mode, link status and

full duplex flow control ability for each port. The

chip provides four modes for phy configurations,

1/53

August 1, 2003

TC9208M-DS-R06

General Description

TC9208M is a fully integrated 8 port 10/100/1000

smart Ethernet switch controller designed for low

cost and high performance solutions. The chip

embeds necessary SSRAM for packet buffering

and MAC address table. It provides MII / GMII

interface for all ports.

A store-and-forward switching method using a

non-blocking architecture is implemented within

TC9208M to improve the availability and

bandwidth. The chip embeds packet buffer, which

it supports normal and priority queues for each

transmission port.

TC9208M provides evolved CoS with four levels

of priority. The priority can be checked via layer 2

(802.1Q VLAN Tagging) and/or layer 3 (IP Header

TOS bits) packets. Port based priority is also

provided to ensure transmission with precedence

for all packets incoming from selected port(s).

Confidential.

TC9208M

Preliminary Data Sheet

Table Of Contents

Features ..............................................................................................................................................................1

General Description ............................................................................................................................................1

Block Diagram.....................................................................................................................................................2

Table Of Contents ...............................................................................................................................................3

Revision History ..................................................................................................................................................4

Pins Placement...................................................................................................................................................5

1 Pin Listing (PBGA 292) ...............................................................................................................................6

2 Ethernet Media Access Controller ............................................................................................................17

2.1

Receive MAC ..................................................................................................................... 17

2.2

Transmit MAC .................................................................................................................... 18

3 MAC Address Handling.............................................................................................................................19

4 Queue Management.................................................................................................................................19

5 Classes of Service ....................................................................................................................................20

6 Trunk Configuration...................................................................................................................................22

7 Flow Control ..............................................................................................................................................22

8 Broadcast Throttling ..................................................................................................................................24

9 Port Mirroring.............................................................................................................................................24

10 Physical Layer Configuration / Polling......................................................................................................25

11 EEPROM Interface ...................................................................................................................................26

11.1

Reprogramming the EEPROM for reconfiguration ............................................................ 26

11.2

EEPROM Address Map ..................................................................................................... 27

11.3

Register Description........................................................................................................... 29

11.3.1

Validation Register ................................................................................................ 29

11.3.2

Port [X] Configuration Register ............................................................................. 31

11.3.3

Port [X] IFG Configuration Register ...................................................................... 33

11.3.4

Flow Control Register ........................................................................................... 34

11.3.5

Backpressure Time Value Register....................................................................... 35

11.3.6

Flow Control Port Base Address Register ............................................................ 36

11.3.7

Trunk Configuration Register ................................................................................ 36

11.3.8

Broadcast Configuration Register......................................................................... 37

11.3.9

IP Priority Mapping Register ................................................................................. 38

11.3.10

VLAN Priority Mapping Register ........................................................................... 39

CoS Bandwidth Register....................................................................................... 40

11.3.11

11.3.12

Reserved Register ................................................................................................ 40

CoS Configuration Register .................................................................................. 41

11.3.13

11.3.14

Port Mirroring Register.......................................................................................... 42

General Configuration Register ............................................................................ 43

11.3.15

11.3.16

Port VLAN Enable Register .................................................................................. 44

11.3.17

VLAN [Y] Register................................................................................................. 45

11.4

Writing / Reading PHY management registers via EEPROM interface............................. 46

11.4.1

Data Write Register............................................................................................... 46

11.4.2

Physical Layer Device Address Register .............................................................. 46

11.4.3

Physical Layer’s Register Address Register......................................................... 47

11.4.4

IO Status Control Register .................................................................................... 47

11.4.5

Data Read Register .............................................................................................. 48

12 Timing Requirements................................................................................................................................49

12.1 GMII / MII Receive Timing Requirements .......................................................................... 49

12.2 GMII / MII Transmit Timing................................................................................................. 49

12.3 PHY Management (MDIO) Timing ..................................................................................... 50

12.4 EEPROM Timing................................................................................................................ 51

13 Electrical Specifications ............................................................................................................................52

Confidential.

3/53

August 1, 2003

TC9208M-DS-R06

TC9208M Related Products

	TC9208M	TC9208M-DS-R05	TC9208M-DS-R06
Description	8-Port 10/100/1000 Smart Ethernet Switch	8-Port 10/100/1000 Smart Ethernet Switch	8-Port 10/100/1000 Smart Ethernet Switch

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