TC55NEM216AFTN55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V
±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
µA
standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
−40°
to 85°C, the TC55NEM216AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATURES
•
•
•
•
•
•
•
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V
±
10%
Power down features using CE
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
−40°
to 85°C
Standby Current (maximum): 20
µA
•
Access Times (maximum):
TC55NEM216AFTN
55
Access Time
CE
Access Time
OE
Access Time
70
70 ns
70 ns
35 ns
55 ns
55 ns
30 ns
•
Package:
TSOP II54-P-400-0.80
(Weight:
g typ)
PIN ASSIGNMENT
(TOP VIEW)
54 PIN TSOP
NC
A3
A2
A1
A0
I/O16
I/O15
V
DD
GND
I/O14
I/O13
UB
CE
OP
R/W
I/O12
I/O11
GND
V
DD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A4
A5
A6
A7
NC
I/O1
I/O2
V
DD
GND
I/O3
I/O4
LB
OE
OP
NC
I/O5
I/O6
GND
V
DD
I/O7
I/O8
A8
A9
A10
A11
A12
NC
PIN NAMES
A0~A17
CE
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power (+5 V)
Ground
No Connection
Option
R/W
OE
LB ,
UB
I/O1~I/O16
V
DD
GND
NC
OP*
*:
OP pin must be open or connected to GND.
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TC55NEM216AFTN55,70
OPERATING MODE
MODE
CE
OE
R/W
H
H
H
L
L
L
H
H
H
*
*
LB
L
H
L
L
H
L
L
H
L
*
H
UB
I/O1~I/O8
Output
High-Z
Output
Input
High-Z
Input
High-Z
High-Z
High-Z
High-Z
High-Z
I/O9~I/O16
Output
Output
High-Z
Input
Input
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
POWER
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDS
I
DDS
L
Read
L
L
L
Write
L
L
L
Output Deselect
L
L
Standby
*
= don't care
H = logic high
L = logic low
H
*
L
L
L
*
*
*
H
H
H
*
*
L
L
H
L
L
H
L
L
H
*
H
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
−0.3~7.0
−0.3*~7.0
−0.5~V
DD
+
0.5
0.6
260
−55~150
−40~85
UNIT
V
V
V
W
°C
°C
°C
*:
−2.0
V when measured at a pulse width of 20ns
DC RECOMMENDED OPERATING CONDITIONS (
Ta
= −
40° to 85°C
)
SYMBOL
V
DD
V
IH
V
IL
V
DH
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
MIN
4.5
2.2
−0.3*
2.0
TYP
5.0
MAX
5.5
V
DD
+
0.3
0.6
5.5
UNIT
V
V
V
V
*:
−2.0
V when measured at a pulse width of 20ns
2002-07-04
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TC55NEM216AFTN55,70
(Ta
= −
40° to 85°C, V
DD
=
5 V
±
10%)
READ CYCLE
TC55NEM216AFTN
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
55
5
0
5
10
55
MAX
55
55
30
55
25
25
25
MIN
70
5
0
5
10
70
MAX
70
70
35
70
30
30
30
ns
UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
TC55NEM216AFTN
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Note:
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
55
40
45
45
0
0
0
25
0
55
MAX
25
MIN
70
50
55
55
0
0
0
30
0
70
MAX
30
ns
UNIT
t
OD
, t
ODO
, t
BD
and t
ODW
are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
AC TEST CONDITIONS
PARAMETER
Input pulse level
t
R
, t
F
Timing measurements
Reference level
Output load
TEST CONDITION
0.4 V, 2.4 V
5 ns
1.5 V
1.5 V
100 pF
+
1 TTL Gate
2002-07-04
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