®
SP7800A
12-Bit 3µs Sampling A/D Converter
s
s
s
s
s
s
s
s
333k Samples Per Second
Standard
±10V
and
±5V
Input
No Missing Codes Over Temperature
AC Performance Over Temperature
71.5dB Signal–to–Noise Ratio at Nyquist
85dB Spurious–free Dynamic Range at
49KHz
–81dB Total Harmonic Distortion at
49KHz
Internal Sample/Hold, Reference,
Clock, and 3-State Outputs
Power Dissipation: 90mW
24–Pin Narrow DIP and 24–Lead SOIC
Enhanced Single (+5V) Supply Version of
ADS7800
DESCRIPTION…
The
SP7800A
is a complete 12-bit sampling A/D converter using state–of–the–art CMOS structures.
It contains a complete 12–bit successive approximation A/D converter with internal sample/hold,
reference, clock, digital interface for microprocessor control, and three–state output drivers. AC and
DC performance are completely specified. Two grades based on linearity and dynamic performance
are available to provide the optimum price/performance fit in a wide range of applications.
CS
R/C HBE
Control
Logic
IBIP
±10V
IN
±5V
IN
Internal
Ref
Clock
SAR
Output
Latches
And
Three
State
Drivers
Comparator
BUSY
CDAC
.....
.....
.....
.....
Three
State
Parallel
Output
Data
Bus
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
© Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
S
to Digital Common ............................................................... +7V
Pin 23 (V
SO
) to Pin 24 (V
SA
) ....................................................
±0.3V
Analog Common to Digital Common ......................................
±0.3V
Control Inputs to Digital Common ....................... –0.3 to V
S
+ 0.3 V
Analog Input Voltage ..............................................................
±20V
Maximum Junction Temperature ........................................... 160°C
Internal Power Dissipation .................................................. 750mW
Lead Temperature (soldering, 10s) ..................................... +300°C
Thermal Resistance. Ø
JA
:
Plastic DIP ....................................................................... 50°C/W
SOIC ............................................................................ 100°CC/W
SPECIFICATIONS
T
A
= 25°C, Sampling Frequency, f
8
, = 333kHz, V
S
= +5V, unless otherwise specified.
PARAMETER
RESOLUTION
ANALOG INPUT
Voltage Ranges
Impedance
±10V
Range
±5V
Range
THROUGHPUT SPEED
Conversion Time
Complete Cycle
Throughput Rate
DC ACCURACY
Full Scale Error
–J
–K
Integral Linearity Error
–J
–K
Differential Linearity Error
–J
–K
No Missing Codes
Bipolar Zero
–J
–K
Power Supply Sensitivity
–J
–K
AC ACCURACY
Spurious-Free Dynamic Range
–J
–K
Total Harmonic Distortion
–J
–K
Two-tone Intermod. Distortion
–J
–K
MIN .
TYP.
MAX .
12
UNITS
BITS
V
CONDITIONS
±10V/±5V
4.7
2.7
6.7
3.9
2.6
3.0
8.7
5.1
2.7
333
kΩ
kΩ
µs
µs
kHz
T
MIN
≤
T
A
≤
T
MAX
T
MIN
≤
T
A
≤
T
MAX
Conversion alone
Acquisition plus conversion
T
MIN
≤
T
A
≤
T
MAX
Note 1
±0.50
±0.35
±1
±
1
⁄2
±1
±
3
⁄4
Guaranteed
±4
±2
±.1
±0.5
%
%
Note 2
LSB
LSB
LSB
LSB
Note 1
LSB
LSB
Note 3
LSB
LSB
T
MIN
≤
T
A
≤
T
MAX
74
77
77
80
–77
–80
–77
–80
–74
–77
–74
–77
dB
dB
dB
dB
dB
dB
Note 4; f
IN
= 47kHz
f
IN
= 47kHz
f
IN1
= 24.4kHz (–6dB); f
IN2
=
28.5kHz (-6dB)
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
© Copyright 2000 Sipex Corporation
2
SPECIFICATIONS (continued)
T
A
= 25°C, Sampling Frequency, f
8
, = 333kHz, V
S
= +5V, unless otherwise specified.
PARAMETER
MIN .
TYP.
MAX .
AC ACCURACY
Signal to (Noise + Distortion) Ratio
–J
67
70
–K
69
71.0
Signal to Noise Ratio (SNR)
–J
68
71
–K
70
71.5
SAMPLING DYNAMICS
Aperture Delay
13
Aperture Jitter
150
Transient Response
–J
130
–K
150
Overvoltage Recovery
150
DIGITAL INPUTS
Logic Levels
V
IL
–0.3
+0.8
V
IH
+2.4
+5.3
I
IL
–5
I
IH
+5
DIGITAL OUTPUTS
Data Format
Parallel; 12-bit or 8-bit/4-bit
Data Coding
Binary; Offset Binary
V
OL
DGND
+0.4
V
OH
+2.4
V
DD
I
LEAKAGE
(High-Z State)
±0.1
±5
POWER SUPPLY REQUIREMENTS
Rated Voltage
+4.75
+5.0
+5.25
Current
18
21
Power Consumption
90
ENVIRONMENTAL AND MECHANICAL
Specification
–J, –K
0
+70
Storage
Package
–_N
–_S
–65
+150
UNITS
dB
dB
dB
dB
ns
ps, rms
CONDITIONS
T
MIN
≤
T
A
≤
T
MAX
f
IN
= 47kHz
f
IN
= 47kHz
Note 5
ns
ns
ns
Note 6
T
MIN
≤
T
A
≤
T
MAX
V
V
µA
µA
V
V
µA
V
mA
mW
I
SINK
= 1.6mA
I
SOURCE
= 1.6mA
V
S
(V
SA
and V
SD
)
I
S
°C
°C
24–pin Narrow DIP
24–pin SOIC
NOTES
1.
Adjustable to zero with external potentiometer.
2.
LSB means Least Significant Bit. For SP7800A, 1LSB = 2.44mV for
±5V
range, 1 LSB = 4.88mV for
±10V
range.
3.
Measured at mid-range, between 4.75 < V
S
< 5.25 volts.
4.
All specifications in dB are referred to a full-scale input, either
±10V
or
±5V.
5.
For full-scale step input, 12-bit accuracy attained in specified time.
6.
Recovers to specified performance in specified time after 2 x F
S
input overvoltage.
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
© Copyright 2000 Sipex Corporation
3
PINOUT
Pin 12 — D
4
— Data Bit 4 if HBE is LOW; LOW if
HBE is HIGH.
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
V
SA
V
SD
N.C.
BUSY
CS
R/C
IN
1
IN
2
N.C.
AGND
D
11
D
10
D
9
D
8
Pin 13 — DGND — Digital Ground. Connect to pin
4 at the device.
Pin 14 — D
3
— Data Bit 3 if HBE is LOW; Data Bit
11 if HBE is HIGH.
Pin 15 — D
2
— Data Bit 2 if HBE is LOW; Data Bit
10 if HBE is HIGH.
Pin 16 — D
1
— Data Bit 1 if HBE is LOW; Data Bit
9 if HBE is HIGH.
Pin 17 — D
0
— Data Bit 0 if HBE is LOW. Least
Significant Bit (LSB). Data Bit 8 if HBE is HIGH.
Pin 18 — HBE — High Byte Enable, When held
LOW, data output as 12-bits in parallel. When held
HIGH, four MSBs presented on pins 14–17, pins 9 –
12 output LOWs. Must be LOW to initiate conver-
sion.
Pin 19 — R/C — Read/Convert. Falling edge initiates
conversion when CS is LOW, HBE is LOW, and
BUSY is HIGH.
Pin 20 — CS — Chip Select. Outputs in Hi-Z state
when HIGH. Must be LOW to initiate conversion or
read data.
Pin 21 — BUSY . Output LOW during conversion.
Data valid on rising edge in Convert Mode.
Pin 22 — N.C. — This pin is not internally connected.
Pin 23 — V
SD
— Positive Digital Power Supply, +5V.
Connect to pin 24, and bypass to DGND.
Pin 24 — V
SA
— Positive Analog Power Supply.
+5V. Connect to pin 23, and bypass to AGND.
SP7800A
18 HBE
17 D
0
16 D
1
15 D
2
14 D
3
13 DGND
D
7
D
6
10
D
5
11
D
4
12
PIN ASSIGNMENT
Pin 1 — IN
1
—
±10V
Analog Input. Connected to
AGND for
±5V
range.
Pin 2 — IN
2
—
±5V
Analog Input. Connected to
AGND for
±10V
range.
Pin 3 — N.C. — This pin is not internally connected.
Pin 4 — AGND — Analog Ground. Connect to pin
13 at the device.
Pin 5 — D
11
— Data Bit 11. Most Significant Bit
(MSB).
Pin 6 — D
10
— Data Bit 10.
Pin 7 — D
9
— Data Bit 9.
Pin 8 — D
8
— Data Bit 8.
Pin 9 — D
7
— Data Bit 7 if HBE is LOW; LOW if
HBE is HIGH.
Pin 10 — D
6
— Data Bit 6 if HBE is LOW; LOW if
HBE is HIGH.
Pin 11 — D
5
— Data Bit 5 if HBE is LOW; LOW if
HBE is HIGH.
FEATURES...
The
SP7800A
is specified at a 333kHz sampling rate.
Conversion time is factory set for 2.70µs max over
temperature, and the high-speed sampling input stage
insures a total acquisition and conversion time of 3µs
max over temperature. Precision, laser–trimmed scal-
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
© Copyright 2000 Sipex Corporation
4
ing resistors provide industry–standard input ranges
of
±5V
or
±10V.
The 24-pin
SP7800A
is available in
plastic DIP, and SOIC packages and it operates from
a single +5V supply. The
SP7800A
is available in
grades specified over the 0°C to +70°C commercial
temperature ranges.
OPERATION...
Basic Operation
Figure 1
shows the simple hookup circuit required
to operate the
SP7800A
in a
±10V
range in the
Convert Mode. A convert command arriving on
R/C, (a pulse taking R/C LOW for a minimum of
40ns) puts the
SP7800A
in the HOLD mode, and
a conversion is started. The falling edge of R/C
establishes the sampling instant of the A/D; it must
therefore have very low jitter. BUSY will be held
LOW during the conversion, and rises only after
the conversion is completed and the data has been
transferred to the output drivers. Thus, the rising
edge can be used to read the data from the conver-
sion. Also, during conversion, the BUSY signal
puts the output data lines in Hi-Z states and inhibits
the input lines. This means that pulses on R/C are
ignored, so that new conversions cannot be initi-
ated during a conversion, either as a result of
spurious signals or to short-cycle the
SP7800A.
In the Read Mode, the input to R/C is kept nor-
mally LOW, and a HIGH pulse is used to read data
and initiate a conversion. In this mode, the rising
+5V
1
Input
2
3
4
5
6
7
8
9
IN 1
IN 2
N.C.
AGND
+5V 24
+5V 23
N.C. 22
BUSY 21
Busy
D11 (MSB)
D10
D9
D8
D7
CS 20
R/C 19
HBE 18
D0 (LSB) 17
D1 16
D2 15
D3 14
DGND 13
D0
(LSB)
Convert
Command
6.8µF +
0.1µF
edge of R/C will enable the output data pins, and
the data from the previous conversion becomes
valid. The falling edge then puts the
SP7800A
in
a hold mode, and initiates a new conversion.
The
SP7800A
will begin acquiring a new sample
just prior to BUSY output rising, and will track the
input signal until the next conversion is started.
For use with an 8-bit bus, the data can be read out
in two bytes under the control of HBE. With a
LOW input on HBE, at the end of a conversion, the
8 LSBs of data are loaded into the output drivers D
7
– D
4
and D
3
–D
0
. Taking HBE HIGH then loads the
4 MSBs on output drivers D
3
–D
0
, with D
7
–D
4
being forced LOW.
Analog Input Ranges
The
SP7800A
offers two standard bipolar input
ranges:
±10V
and
±5V.
If a
±10V
range is re-
quired, the analog input signal should be con-
nected to pin 1. A signal requiring a
±5V
range
should be connected to pin 2. In either case, the
other pin of the two must be grounded or connected
to the adjustment circuits described in the section
on calibration.
Controlling The SP7800A
The
SP7800A
can be easily interfaced to most
microprocessor-based and other digital systems. The
microprocessor may take full control of each conver-
sion, or the
SP7800A
may operate in a stand-alone
mode, controlled only by the R/C input. Full control
consists of initiating the conversion and reading the
output data at user command, transmitting data either
all 12-bits in one parallel word, or in two 8-bit bytes.
The three control inputs (CS, R/C and HBE) are all
TTL/CMOS compatible. The functions of the control
lines are shown in
Table 1.
For stand-alone operation, control of the
SP7800A
is accomplished by a single control line connected
to R/C. In this mode, CS and HBE are connected
to GND. The output data are presented as 12-bit
words. The stand-alone mode is used in systems
containing dedicated input ports which do not
require full bus interface capability.
Conversion is initiated by a HIGH-to-LOW transition
10 D6
11 D5
12 D4
D11
(MSB)
Data
Out
Figure 1. Basic
±10V
Operation
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
© Copyright 2000 Sipex Corporation
5
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