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DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD784927, 784928, 784927Y, 784928Y
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-
speed, high-performance 16-bit CPU for VCR software servo control.
The
µ
PD784927Y and 784928Y are based on the
µ
PD784928 with the addition of an I
2
C bus interface compatible
with multi-master.
They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer
unit) for software servo control and VCR analog circuits.
Flash memory models, the
µ
PD78F4928 and
µ
PD78F4928Y, are under development.
The functions of the
µ
PD784927 is described in detail in the following User’s Manual. Be sure to read this
manual before designing your system.
µ
PD784928, 784928Y Subseries User’s Manual - Hardware
78K/IV Series User’s Manual - Instruction
: U12648E
: U10905E
FEATURES
•
•
High instruction execution speed realized by 16-bit CPU core
• Minimum instruction execution time: 250 ns (with 8 MHz internal clock)
High internal memory capacity
Item
Part Number
µ
PD784927, 784927Y
96K bytes
2048 bytes
µ
PD784928, 784928Y
128K bytes
3584 bytes
Internal ROM capacity
Internal RAM capacity
•
VCR analog circuits conforming to VHS Standard
• CTL amplifier
• RECCTL driver (rewritable)
• CFG amplifier
• DFG amplifier
• DPG amplifier
• Reel FG comparator (2 channels)
• CSYNC comparator
• DPFG separation circuit (ternary separation circuit)
•
•
•
•
•
•
•
•
•
Timer unit (super timer unit) for servo control
Serial interface : 3 channels
3-wire serial I/O : 2 channels
I
2
C bus interface: 1 channel
A/D converter: 12 channels (conversion time: 10
µ
s)
Low-frequency oscillation mode: main system clock frequency = internal clock frequency
Low-power consumption mode: CPU can operate with a subsystem clock.
Supply voltage range: V
DD
= +2.7 to 5.5 V
Hardware watch function: watch operation at low voltage (V
DD
= 2.7 V (MIN.)) and low current consumption
Unless otherwise specified, the
µ
PD784927 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12255EJ2V1DS00 (2nd edition)
Date Published October 2005 N CP(K)
Printed in Japan
The mark
shows major revised points.
1997, 1999
FPGA/CPLD
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