EM MICROELECTRONIC
- MARIN SA
EM6617
Ultra Low Power Microcontroller with ADC AND EEPROM
Features
•
Low Power
- 3.2 µA active mode, ADC off
- 9.0 µA active mode, ADC on
- 0.6 µA standby mode
- 0.1µA sleep mode
@ 3.0V, 32kHz, 25°C
Voltage range logic incl. EEPROM 2.0 to 5.5 V
System operating clock : 32 or 128KHz (metal option)
Voltage range for the ADC is 2.6 to 5.5 V
2 clocks per instruction cycle
72 basic instructions
ROM
3k
×
16 bit
RAM
128
×
4 bit
2
E PROM 64
×
8 bit
Voltage Level Detector, 3 levels software
selectable :2.2, 2.5, 3.0 V
2 channel ADC, successive approximation method;
conversion time at 32 kHz : 305µs
Max. 12 inputs (3 ports); port A, port B, port C
Max. 8 outputs (2 ports); port B, port C
Serial Write Buffer, 256 bit wide , 4 bit rates
Oscillation supervisor and timer watchdog
Universal 10-bit counter, PWM, event counter
8 internal interrupt sources (2
×
timer , 2
×
prescaler,
ADC, VLD, FIFO, EEPROM)
4 external interrupt sources (input port A )
Frequency output; 32kHz, 2kHz, 1kHz, PWM
Figure 1. Architecture
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Figure 2. Pin Configuration
Description
The EM6617 is an advanced single chip CMOS 4-bit
microcontroller. It contains ROM, RAM, power on reset,
watchdog timer, oscillation detection circuit, combined
2
timer , event counter, prescaler, E PROM, 2 channel ADC,
serial write buffer, voltage level detector and several clock
functions. The low voltage feature and low power
consumption make it the most suitable controller for
battery, stand alone and mobile equipment. The EM6617
is manufactured using EM Microelectronic’s advanced low
power (ALP) CMOS Process.
Typical Applications
•
•
•
•
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•
•
•
Sensor & detector interface
Heat meter interface
Security systems
Household equipment controls
Automotive controls
Measurement equipment
R/F and IR. control
Voltage control
03/02 REV. C/442
Copyright
2002, EM Microelectronic-Marin SA
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EM6617
EM6617 at a glance
• Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 2.0 ... 5.5 V battery voltage for all logic functions
- 2.6 ... 5.5 V battery voltage for the ADC (0.2LSB)
- 3.2 µA in active mode, ADC off
• 2 Channel 8-bit ADC
- Conversion time is 305
µs
@32kHz
- 2 operating modes (continuous, single)
- Interrupt request at the end of conversion
- 9.0 µA active mode, ADC on
- 0.6µA in standby mode
- 0.1µA in sleep mode
- 32 KHz crystal oscillator
• Prescaler
- 15 stage system clock divider down to 1 Hz
- 2 Interrupt requests; 1 Hz, 32 Hz or 8 Hz
- Prescaler reset (4 KHz to 1Hz)
• RAM
- 64 x 4 bit, direct addressable
- 64 x 4 bit, indirect addressable
• 4-Bit Bi-directional Port B
- All different functions bit-wise selectable
- Direct input read on the port terminals
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
- Selectable PWM, 1kHz, 32kHz and 2kHz output
• ROM
- 3072 x 16 bit metal mask programmable
• E
2
PROM
- 64 x 8 bit, indirect addressable
- Interrupt request at the end of a write operation
• 4Bit Bi-directional Port C
- Input or output mode as whole port
- Direct input read on port terminal
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
• CPU
- 4 bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
• Main Operating Modes and Resets
- Active Mode (CPU is running)
- Standby Mode (CPU in halt)
- Sleep Mode (No clock, reset state)
- Initial reset on power on (POR)
- Watchdog resets (logic and oscillation watchdogs)
- Reset terminal
- Reset with input combination on port A register
selectable, ¨AND¨ or ¨OR¨ type by metal mask
• Voltage Level Detector
- 3 levels software selectable (2.0, 2.5, 3.0 V)
- Busy flag during measure
- Interrupt request at end of measure
• 10-Bit Universal Counter
- 10, 8, 6 or 4bit up/down counting
- Parallel load
- 8 different input clocks
- Event counting (PA[0] or PA[3] )
- Full 10 bit or limited (8, 6, 4 bit) compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[3] and PA[0]
- Pulse-width modulation (PWM) output
• 4-Bit Input Port A
- Direct input read on the port terminals
- Debouncer function available on all inputs
- Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by register
- Test variables (software) for conditional jumps
- PA[0] and PA[3] are inputs for the event counter
- Reset with input combination (register selectable)
• Interrupt Controller
- 4 external and 8 internal interrupt request sources
- Each interrupt can individually be maskable
- Each interrupt can individually be reset
- Automatic reset of each interrupt request after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request flag
when going into HALT mode
• Serial Write Buffer (output)
- Max 256 bits long bit rates of 16kHz,8kHz,2kHz,1kHz
- Automatic or interactive send mode
- Interrupt request when buffer is empty
03/02 REV. C/442
Copyright
2002, EM Microelectronic-Marin SA
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EM6617
Table of Contents
F
EATURES
1
D
ESCRIPTION
________________________________ 1
TYPICAL
APPLICATIONS
_______________________ 1
EM6617
AT A GLANCE
_________________________ 2
1. Pin Description for EM6617 _________________ 4
2. Typical configurations _____________________ 5
3. Operating Modes _________________________ 6
3.1
Active Mode _________________________ 6
3.2
Standby Mode________________________ 6
3.3
Sleep Mode__________________________ 6
4. Power Supply ____________________________ 7
5. Reset __________________________________ 8
5.1
Oscillation Detection Circuit _____________ 9
5.2
Reset Terminal _______________________ 9
5.3
Input Port A Reset Function _____________ 9
5.3.1
AND-Type Reset function ___________ 9
5.3.2
OR -Type Reset function ___________ 10
5.4
Digital Watchdog Timer Reset __________ 10
5.5
CPU State after Reset ________________ 11
6. Oscillator and Prescaler___________________ 12
6.1
Oscillator___________________________ 12
6.2
Prescaler___________________________ 12
7. Input and Output ports ____________________ 13
7.1
Ports overview ______________________ 13
7.2
Port A _____________________________ 14
7.2.1
IRQ on Port A ___________________ 14
7.2.2
Pull-up or Pull-down ______________ 15
7.2.3
Software Test Variables ___________ 15
7.2.4
Port A for 10-Bit Counter ___________ 15
7.3
Port A registers ______________________ 15
7.4
Port B _____________________________ 17
7.4.1
Input / Output Mode_______________ 17
7.4.2
Pull-up or Pull-down ______________ 18
7.4.3
CMOS or Nch. Output _____________ 18
7.4.4
PWM and Frequency Output________ 19
7.5
Port B registers ______________________ 19
7.6
Port C _____________________________ 19
7.6.1
Pull-up or Pull-down ______________ 20
7.6.2
CMOS or Nch. Output _____________ 21
7.7
Port C Registers _____________________ 21
8. 10-bit Counter __________________________ 23
8.1
Full and Limited Bit Counting ___________ 23
8.2
Frequency Select and Up/Down Counting _ 24
8.3
Event Counting ______________________ 25
8.4
Compare Function ___________________ 25
8.5
Pulse Width Modulation (PWM) _________ 25
8.5.1
How the PWM Generator works._____ 26
8.5.2
PWM Characteristics______________ 26
8.6
Counter Setup_______________________ 27
8.7
10-bit Counter Registers_______________ 27
9. Serial (Output) Write Buffer - SWB __________ 29
9.1
SWB Automatic send mode ____________29
9.2
SWB Interactive send mode ____________31
9.3
SWB registers _______________________32
10.
2-Channel ADC (8-bit digital converter) _____33
10.1 Continuous mode ____________________34
10.2 Single mode ________________________34
10.3 2-Channel ADC registers ______________35
11.
EEPROM ( 64
×
8 Bit ) __________________36
11.1 EEPROM registers ___________________37
12.
Supply Voltage Level Detector ____________38
12.1 SVLD Register_______________________38
13.
Interrupt Controller _____________________39
13.1 Interrupt control registers ______________40
14.
RAM ________________________________41
15.
Strobe Output _________________________42
15.1 Strobe register_______________________42
16.
PERIPHERAL MEMORY MAP ____________43
17.
Option Register Memory Map _____________46
18.
Active Supply Current Test _______________47
19.
Mask Options _________________________48
19.1 Input / Output Ports ___________________48
19.1.1 Port A Metal Options ______________48
19.1.2 Port B Metal Options ______________49
19.1.3 Port C Metal Options ______________50
19.1.4 SWB high impedance state _________51
19.1.5 Debouncer Frequency Option _______51
19.1.6 System Frequency ________________51
19.1.7 Additional mask options ____________51
20.
Temp. and Voltage Behavior _____________52
20.1 I(VDD) Current ______________________52
20.2 IOL, IOH ___________________________53
20.3 Pull-up, Pull-down ____________________54
20.4 Vreg, EEPROM ______________________54
20.5 ADC8______________________________55
21.
Electrical Specification __________________57
21.1 Absolute Maximum Ratings ____________57
21.2 Handling Procedures__________________57
21.3 Standard Operating Conditions __________57
21.4 DC Characteristics - Power Supply _______58
21.5 Oscillator ___________________________58
21.6 DC characteristics - I/O Pins ____________59
21.7 Supply Voltage Level Detector __________60
21.8 ADC 8 Bit___________________________60
21.9 EEPROM___________________________60
22.
Pad Location Diagram __________________61
23.
Package & Ordering information___________62
23.1 Ordering Information __________________65
23.2 Package Marking ____________________65
23.3 Customer Marking____________________65
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than
circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves
the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure
that the information given has not been superseded by a more up-to-date version.
03/02 REV. C/442
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EM6617
1. Pin Description for EM6617
PDIP24
SO24
17
21
18
15
14
16
19
20
10
11
12
13
6
7
5
8
4
9
-
-
22
23
24
1
PDIP28
SO28
TSSOP28
20
24
21
18
17
19
22
23
13
14
15
16
7
8
6
9
5
10
4
12
25
26
27
28
Signal Name
Function
Remarks
V
BAT=
V
DD
V
SS
Vreg
Test
Reset
Strobe
Qin
Qout
PB[0]
PB[1]
PB[2]
PB[3]
PA[0]
PA[1]
PA[2]
PA[3]
PC[0]
PC[1]
PC[2]
PC[3]
Ain
Bin
Vref
Vgnd
Positive power supply
Negative power supply
Internal voltage regulator
Input test terminal,
internal pull-down 15k
Reset terminal
internal pull-down 15k
Strobe / reset status
Crystal terminal 1
Crystal terminal 2
Input or output, CMOS or Nch.
open drain; port B terminal 0
Input or output, CMOS or Nch.
open drain; port B terminal 1
Input or output, CMOS or Nch.
open drain; port B terminal 2
Input or output, CMOS or Nch.
open drain; port B terminal 3
Input port A terminal 0
Input port A terminal 1
Input port A terminal 2
Input port A terminal 3
Input or output, CMOS or Nch.
open drain; port C terminal 0
Input or output, CMOS or Nch.
open drain; port C terminal 1
Input or output, CMOS or Nch.
open drain; port C terminal 2
Input or output, CMOS or Nch.
open drain; port C terminal 3
channel A for A/D converter
channel B for A/D converter
external voltage reference input
FOR the A/D converter
Virtual analogue ground for A/D
converter
Main power pin
MFP programming connection
Reference terminal, substrate
MFP programming connection
connect to minimum 100nF
MFP programming connection
for EM tests only, ground 0 !
Except for MFP programming
µC reset state + port B write
32kHz crystal
MFP programming connection
32kHz crystal
MFP programming connection
Ck[12] output (2 KHz)
Ck[16] output (32 KHz)
Ck[11] output (1 KHz)
PWM output
TestVar 1,
event counter
TestVar 2
Event counter
Bonded only in 28 pin package
Bonded only in 28 pin package
Only used for external Vref
i.e. Vref not equal to V
DD
Virtual Ground, usually V
DD
/2
2
2
Data
Serial write buffer data out
3
3
Clk
Serial write buffer clock out
Gray shaded area : MFP programming connections (V
DD
, Vreg, Qin , Qout, Test, Vss).
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EM6617
2. Typical configurations
Full range ADC :
Vref = V
DD
, Vgnd = V
DD
/2.
For power saving one might connect the Vgnd resistor divider chain onto a port B output. This output should be
driving V
DD
during the conversion and driving V
SS
or high impedance in the ADC off state.
Figure 3. Typical Application, Full Range
Main power
V
DD
Vgnd
Vss
Full
range
ADC
32 KHz
Reset
Strobe
Port A
Port B
Port C
Vgnd
R1
Vss
Bin
Vref
V
DD
R1
V
DD
Vreg V
SS
Ain
+
-
≈
Vss
V
DD
, or port driven
>1.3V
Limited range ADC :
V
DD
> Vref > Vgnd, Vgnd=V
DD
/2.
For power saving one might connect the Vgnd and the Vref resistor divider chain onto a port B output to V
SS
.
This output should be driving V
DD
during the conversion and driving Vss or high impedance in the ADC off state.
Figure 4. Typical Application, Limited Range
Main power
+| Vref - Vgnd |
Vdd
Vref
Vgnd
Vss
32 KHz
Reset
Strobe
Port A
Port B
Port C
V
DD
Vreg Vss
Ain
Bin
Vref
Vref
limited
range
ADC
+
-
≈
Vss or Vgnd
R1
-| Vref - Vgnd |
Vdd or Port B driven
>1.3V
C1
Vss
Vgnd
R1
other possibility:
VREF = VregLogic, VGND = VregLogic/2
For power saving one might connect the Vgnd resistor divider chain from VregLogic onto a port B output. This
output should be driving V
SS
during the conversion and driving ‘high impedance’ in the ADC off state.
03/02 REV. C/442
Copyright
2002, EM Microelectronic-Marin SA
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