MOSEL VITELIC
V54C3128(16/80/40)4(BGA)
128Mbit SDRAM
3.3 VOLT, BGA PACKAGE
8M X 16
16M X 8
32M X 4
6
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
166 MHz
6 ns
5.4 ns
5.4 ns
PRELIMINARY
7
143 MHz
7 ns
5.4 ns
6 ns
8PC
125 MHz
8 ns
6 ns
6 ns
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
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Features
4 banks x 2Mbit x 16 organization
4 banks x 4Mbit x 8 organization
4 banks x 8Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 60 Pin WBGA
LVTTL Interface
Single +3.3 V
±
0.3 V Power Supply
Description
The V54C3128(16/80/40)4(BGA) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4(BGA) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
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Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
Package Outline
B
•
Access Time (ns)
6
•
Power
8PC
•
7PC
•
7
•
Std.
•
L
•
Temperature
Mark
Blank
V54C3128(16/80/40)4(BGA) Rev. 1.1 August 2001
1
MOSEL VITELIC
V 54
MOSEL-VITELIC
MANUFACTURED
SYCHRONOUS
DRAM FAMILY
C = CMOS PROCESS
3.3V, LVTTL, INTERFACE
V54C3128(16/80/40)4(BGA)
C
3
128404
V
B
SPEED
8Mbit x 16: 128164
16Mbit x 8: 128804
32Mbit x 4: 128404
6 ns
7 ns
8 ns
B = WBGA
DEVICE
NUMBER
V = LVTTL
SPECIAL FEATURE
COMPONENT REV. LEVEL
PKG.
Description
WBGA
Pkg.
B
Pin Count
60
60 Pin WBGA PIN CONFIGURATION
Top View
9 8 7
A
B
C
D
E
F
G
H
J
K
L
M
3 2 1
9
VCCQ
DQ1
DQ3
DQ5
DQ7
NC
8
DQ0
VSSQ
VCCQ
VSSQ
NC
VCC
CAS
CS
BA0
A10/AP
A1
A3
7
VCC
DQ2
DQ4
DQ6
NC
LDQM
WE
RAS
BA1
A0
A2
VCC
x16
A
B
C
D
E
F
G
H
J
K
L
M
3
VSS
DQ13
DQ11
DQ9
NC
UDQM
NC
CKE
A9
A7
A5
VSS
2
DQ15
VCCQ
VSSQ
VCCQ
NC
VSS
CLK
A12
A11
A8
A6
A4
1
VSSQ
DQ14
DQ12
DQ10
DQ8
Vref
9
VCCQ
NC
NC
NC
NC
NC
8
DQ1
VSSQ
VCCQ
VSSQ
NC
VCC
CAS
CS
BA0
A10/AP
A1
A3
7
VCC
DQ1
DQ2
DQ3
NC
NC
WE
RAS
BA1
A0
A2
VCC
x8
A
B
C
D
E
F
G
H
J
K
L
M
3
VSS
DQ6
DQ5
DQ4
NC
DQM
NC
CKE
A9
A7
A5
VSS
2
DQ7
VCCQ
VSSQ
VCCQ
NC
VSS
CLK
A12
A11
A8
A6
A4
1
VSSQ
NC
NC
NC
NC
Vref
9
VCCQ
NC
NC
NC
NC
NC
8
NC
VSSQ
VCCQ
VSSQ
NC
VCC
CAS
CS
BA0
A10/AP
A1
A3
7
VCC
DQ0
NC
DQ1
NC
NC
WE
RAS
BA1
A0
A2
VCC
x4
A
B
C
D
E
F
G
H
J
K
L
M
3
VSS
DQ3
NC
DQ2
NC
DQM
NC
CKE
A9
A7
A5
VSS
2
NC
VCCQ
VSSQ
VCCQ
NC
VSS
CLK
A12
A11
A8
A6
A4
1
VSSQ
NC
NC
NC
NC
Vref
V54C3128(16/80/40)4(BGA) Rev. 1.1 August 2001
2
MOSEL VITELIC
Capacitance*
T
A
= 0 to 70
°
C, V
CC
= 3.3 V
±
0.3 V, f = 1 Mhz
Symbol Parameter
C
I1
C
I2
C
IO
C
CLK
Input Capacitance (A0 to A11)
Input Capacitance
RAS, CAS, WE, CS, CLK, CKE, DQM
Output Capacitance (I/O)
Input Capacitance (CLK)
V54C3128(16/80/40)4(BGA)
Absolute Maximum Ratings*
Max. Unit
3.8
3.8
pF
pF
Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (V
CC
+0.3) V
Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
6
3.5
pF
pF
*
Note:
Capacitance is sampled and not 100% tested.
Block Diagram
x16 Configuration
Column Addresses
A0 - A8, AP, BA0, BA1
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Bank 1
4096 x 512
x 16 bit
4096 x 512
x16 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 512
x 16 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 512
x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
16
LDQM
WE
UDQM
CKE
RAS
CLK
CAS
CS
V54C3128(16/80/40)4(BGA) Rev. 1.1 August 2001
3
MOSEL VITELIC
Block Diagram
x8 Configuration
Column Addresses
A0 - A9, AP, BA0, BA1
V54C3128(16/80/40)4(BGA)
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Column decoder
Sense amplifier & I(O) bus
4096 x 1024
x 8 bit
4096 x 1024
x 8 bit
4096 x 1024
x 8 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 1024
x 8 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
8
CKE
RAS
CAS
WE
CS
DQM
CLK
V54C3128(16/80/40)4(BGA) Rev. 1.1 August
4
MOSEL VITELIC
Block Diagram
x4 Configuration
Column Addresses
A0 - A9, A11, AP, BA0, BA1
V54C3128(16/80/40)4(BGA)
Row Addresses
A0 - A11, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank 1
Row decoder
Memory array
Bank 2
Row decoder
Memory array
Bank 3
Bank 0
Column decoder
Sense amplifier & I(O) bus
4096 x 2048
x 4 bit
4096 x 2048
x 4 bit
4096 x 2048
x 4 bit
Column decoder
Sense amplifier & I(O) bus
4096 x 2048
x 4 bit
Input buffer
Output buffer
Control logic & timing generator
I/O
1
-I/O
4
CKE
RAS
CAS
WE
CS
DQM
CLK
V54C3128(16/80/40)4(BGA) Rev. 1.1 August 2001
5
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