K4J55323QF-GC
256M GDDR3 SDRAM
256Mbit GDDR3 SDRAM
Revision 1.8
April 2005
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
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2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
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Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.8 (Apr. 2005)
K4J55323QF-GC
Revision History
Revision 1.8 (April 9, 2005)
- Modified note description for the Write Latency on page 47.
256M GDDR3 SDRAM
Revision 1.7 (Jan. 18 , 2005)
- Added Lead Free package part number in the data sheet.
Revision 1.6 (Dec 2 , 2004)
- Changed ICC2P and ICC6 for all frequency. Separted ICC6 for -GC and -GL.
Revision 1.5 (Oct 5 , 2004)
- Added K4J55323QF-G(V)C15
- Timing diagram corrected on page 28
Revision 1.4 (July 9 , 2004)
- Added K4J55323QF-G(V)L20 which is VDD&VDDQ=1.8V(typical)
Revision 1.3 (June 14 , 2004)
- Changed DC spec value for all the frequency. Refer to the DC characteristics of page 45.
- Removed -GC12 from the spec.
Revision 1.2 (February 18 , 2004)
- Changed VDD/VDDQ from 1.9V+ 0.1V to 2.0V+ 0.1V in all frequencies.
- DC changes : Refer to the DC characteristics of page 45.
Revision 1.1 (January 29 , 2004)
- Typo corrected
Revision 1.0 (January 15 , 2004)
- Changed VDD/VDDQ of K4J55323QF-GC12 from 2.1V+ 0.1V to 1.9V+ 0.1V
- Changed VDD/VDDQ of K4J55323QF-GC14/16/20 from 1.8V+ 0.1V to 1.9V+ 0.1V
- Changed tCK(max) from 3.0ns to 3.3ns
- DC spec finalized. Typo corrected
- 2 -
Rev 1.8 (Apr. 2005)
K4J55323QF-GC
Revision History
Revision 0.5 (January 7 , 2004)
- Preliminary spec
- Added "Dummy MRS" command during the power-up sequence. Typo corrected
256M GDDR3 SDRAM
Revision 0.4 (December 10 , 2003)
- Preliminary spec
- Typo corrected
- Added K4J55323QF-GC12 (800MHz) in the spec
- Key AC parameter changes : Refer to the AC spec table on page 46,47
. Added tDAL in the AC characteristics table,
. Added AC parameter of -GC12 in the AC characteristics table,
. Changed tRC of -GC14 from 31tCK to 30tCK,
. Changed tRFC of -GC16 from 34tCK to 33tCK,
- DC changes : Refer to the DC characteristics table of page 45.
- Capacitance table change : Refer to the Capacitance table of page 45.
Revision 0.3 (November 13, 2003)
- Target Spec
- Typo corrected
- Removed 800MHz from the spec
- Changed ICC6 from 4mA to 7mA
- Key AC parameter changes : Refer to the AC spec table on page 46,47
. Changed tWR of -GC14 from 6tCK to 9tCK,
. Changed tWR of -GC16 from 5tCK to 8tCK,
. Changed tWR of -GC20 from 4tCK to 6tCK
. Changed tPDEX and tXSR at low power from 100tCK to 300tCK
Revision 0.2 (October 17, 2003)
- Target Spec
- Typo corrected
Revision 0.1 (September 26, 2003)
- Target Spec
- Typo corrected
Revision 0.0 (September 25, 2003)
- Target Spec
- 3 -
Rev 1.8 (Apr. 2005)
K4J55323QF-GC
256M GDDR3 SDRAM
2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FEATURES
• 2.0V + 0.1V power supply for device operation
• 2.0V + 0.1V power supply for I/O interface
• On-Die Termination (ODT)
• Output Driver Strength adjustment by EMRS
• Calibrated output drive
• Pseudo Open drain compatible inputs/outputs
• 4 internal banks for concurrent operation
• Differential clock inputs (CK and CK)
• Commands entered on each positive CK edge
• CAS latency : 5, 6, 7, 8 and 9 (clock)
• Additive latency (AL): 0 and 1 (clock)
• Programmable Burst length : 4
• Programmable Write latency : 1, 2, 3, 4, 5 and 6 (clock)
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
• RDQS edge-aligned with data for READs
• WDQS center-aligned with data for WRITEs
• Data Mask(DM) for masking WRITE data
• Auto & Self refresh mode
• Auto Precharge option
• 32ms, auto refresh (4K cycle)
• 144 Ball FBGA
• Maximum clock frequency up to700MHz
• Maximum data rate up to 1.4Gbps/pin
• DLL for outputs
ORDERING INFORMATION
Part NO.
K4J55323QF-GC14
K4J55323QF-GC15
K4J55323QF-GC16
K4J55323QF-GC20*
Max Freq.
700MHz
667MHz
600MHz
500MHz
Max Data Rate
1400Mbps/pin
1334Mbps/pin
1200Mbps/pin
1000Mbps/pin
Pseudo
Open Drain
144 - Ball FBGA
Interface
Package
*K4J55323QF-GL20/VL20 : VDD & VDDQ = 1.8V+0.1V(1.7V ~ 1.9V)
*K4J55323QF-V is the Lead Free package part number
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
The 8Mx32 GDDR3 is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words
by 32 bits, fabricated with SAMSUNG
’s
high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 5.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
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Rev 1.8 (Apr. 2005)
K4J55323QF-GC
PIN CONFIGURATION
Normal Package (Top View)
2
3
4
VSSQ
VDDQ
VSSQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
A10
A11
256M GDDR3 SDRAM
5
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
/RAS
BA0
6
DQ2
DQ1
VSSQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
RFU
2
RESET
/CAS
7
DQ0
VDDQ
VDD
VSS
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
VDD
CKE
CK
8
DQ31
VDDQ
VDD
VSS
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
VDD
RFU5
/CK
9
DQ29
DQ30
VSSQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
RFU
1
ZQ
/WE
10
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
/CS
BA1
11
VSSQ
VDDQ
VSSQ
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
A9
A8/AP
12
13
B
WDQS0
RDQS0
C
D
E
F
G
DQ4
DQ6
DQ7
DQ17
DQ19
DM0
DQ5
RFU3
DQ16
DQ18
RDQS3
WDQS3
DM3
DQ26
RFU4
DQ15
DQ13
RDQS1
DQ27
DQ25
DQ24
DQ14
DQ12
WDQS1
H
WDQS2
RDQS2
J
K
L
M
N
DQ20
DQ21
DQ23
VREF
A0
DM2
DQ22
A3
A2
A1
DM1
DQ9
A4
A5
A6
DQ11
DQ10
DQ8
VREF
A7
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. (M,13) VREF for CMD and ADDRESS
4. (M,2) VREF for Data input
- 5 -
Rev 1.8 (Apr. 2005)