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8203-24VPCNSGIT

Description
PDSO4
CategoryAnalog mixed-signal IC    The signal circuit   
File Size160KB,2 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

8203-24VPCNSGIT Overview

PDSO4

8203-24VPCNSGIT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid113239739
package instructionSON, DILCC4,.12
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-N4
JESD-609 codee3
Humidity sensitivity level1
Number of terminals4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Encapsulate equivalent codeDILCC4,.12
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply1.8/3.3 V
Certification statusNot Qualified
Maximum supply current (Isup)2.2 mA
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formNO LEAD
Terminal pitch2.54 mm
Terminal locationDUAL
CrystalFree™ Oscillator
Ultra Low Power Oscillators
8203
PRELIMINARY DATA SHEET
Features
Frequency Range:
Output Type:
Frequency Tolerance:
Supply Voltage:
Power Consumption:
Standby Current:
Standard Package:
Operating Temperature:
6 to 133MHz
CMOS
± 2000 ppm
1.8v - 3.3v
1.9 mA
(@ 1.8v)
<1 uA
5.0 x 3.2 mm
2.5 x 2.0 mm
0 to 70 °C , -20 to 70 °C
-20 to 85 °C, -40 to 85 °C
Specifications
2.5v
6 to 133 MHz
± 2000ppm
This product is rated “Green”, please contact
factory for environmental compliancy information
Specification
Parameter
Supply Voltage
Output Frequency
Frequency Stability
Supply Current
Quiescent Current
Input LOW level
Input HIGH level
Output LOW level
Output HIGH level
Rise/Fall Time
Symbol
VDD
F
OUT
F
STB
IDD
I
STBY
V
IL
V
IH
V
OL
V
OH
T
R
/T
F
1.8v
3.3v
Conditions
VDD ±10%
See ordering code
Total Frequency Stability over temperature, supply variation, aging (1st year at 25°C)
2.0 mA
2.2 mA
Typical; No load condition; 25°C
1 uA (max)
STBY# = GND
0.3 VDD (max)
At STBY# pin
0.7 VDD (min)
0.1 VDD (max)
I
OL
= - 1mA
0.9 VDD (min)
I
OH
= 1mA
2.75ns
2.3 ns
1.9 ns
20% to 80% x VDD. Output load (CL) = 4pF
45% / 55%
For frequencies < 80MHz;
SYM
Symmetry
40% / 60%
For frequencies > 80MHz;
Start-up time
T
ST
4100 us
Output valid time after VDD meets the specified range & STBY# transition
Period Jitter
PJ
RMS
17 ps
6 ps
5 ps
4pF load; 75MHz
Cycle to Cycle Jitter
CCJ
MAX
120 ps
4pF load; 75MHz
50 ps
40 ps
Note: Above specifications are typical unless otherwise specified.
* Stability over temperature, supply variation, 3x reflow, load variation, aging (10 years)
1.9 mA
Package Outline and Dimensions
3.20 ±0.05
0.90 ±0.05
1.20 ±0.05
Pin #1 ID
Chamfer
0.5 x 45°
0.85 ±0.05
0.0-0.05
Typical PCB Land Pattern
2.2
5.0 x 3.2
(mm)
STBY#
5.0 x 3.2mm
VDD
2.5
4L SMD
5.00 ±0.05
2.54
GND
0.203 Ref.
OUT
1.4
1.6
Top View
2.0 ±0.05
Bottom View
0.65 ±0.05
0.75 ±0.05
Pin #1 ID
Chamfer
0.35 x 45°
Side View
1.5
0.0-0.05
0.55 ±0.05
2.5 x 2.0
(mm)
STBY#
1.8
VDD
OUT
0.8
2.5 x 2.0mm
4L SMD
2.5 ±0.05
1.225 Bsc
0.152 Ref.
GND
0.9
0.9
Top View
Bottom View
Side View
June 1, 2011
www.IDT.com
©2011 Integrated Device Technology, Inc
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