C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Full Speed USB Flash MCU Family
Analog Peripherals
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10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only)
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HIgh Speed 8051 µC Core
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Pipelined instruction architecture; executes 70% of
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Memory
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4352 or 2304 Bytes RAM
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64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Instructions in 1 or 2 system clocks
48 MIPS and 25 MIPS versions available.
Expanded interrupt handler
Up to 200 ksps
Built-in analog multiplexer with single-ended and
differential mode
VREF from external pin, internal reference, or V
DD
Built-in temperature sensor
External conversion start input option
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USB Function Controller
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USB specification 2.0 compliant
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Full speed (12 Mbps) or low speed (1.5 Mbps) operation
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Integrated clock recovery; no external crystal required for
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On-Chip Debug
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On-chip debug circuitry facilitates full speed, non-intru-
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sive in-system debug (No emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
full speed or low speed
Supports eight flexible endpoints
1 kB USB buffer memory
Integrated transceiver; no external resistors required
Two comparators
Internal voltage reference
(C8051F340/1/2/3/4/5/6/7/A/B only)
Brown-out detector and POR Circuitry
Digital Peripherals
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40/25 Port I/O; All 5 V tolerant with high sink current
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Hardware enhanced SPI™, SMBus™, and one or two
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enhanced UART serial ports
Four general purpose 16-bit counter/timers
16-bit programmable counter array (PCA) with five cap-
ture/compare modules
External Memory Interface (EMIF)
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Clock Sources
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Internal Oscillator: ±0.25% accuracy with clock recovery
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enabled. Supports all USB and UART modes
External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
Low Frequency (80 kHz) Internal Oscillator
Can switch between clock sources on-the-fly
Voltage Supply Input: 2.7 to 5.25 V
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Voltages from 3.6 to 5.25 V supported using On-Chip
Voltage Regulator
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Packages
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48-pin TQFP (C8051F340/1/4/5/8/C)
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32-pin LQFP (C8051F342/3/6/7/9/A/B/D)
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5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
X
DIGITAL I/O
CROSSBAR
UART0
UART1*
SPI
SMBus
PCA
4 Timers
48 Pin Only
Port 0
Ext. Memory I/F
Port 1
Port 2
Port 3
Port 4
10-bit
200 ksps
ADC
+
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+
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TEMP
SENSOR
VREG
VREF
C8051F340/1/2/34/5/6/7/A/B Only
* C8051F340/1/4/5/8/A/B/C Only
PRECISION INTERNAL
OSCILLATORS
USB Controller /
Transceiver
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(48/25 MIPS)
DEBUG
CIRCUITRY
4/2 kB RAM
POR
WDT
Rev. 1.4 9/09
Copyright © 2009 by Silicon Laboratories
C8051F34x
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
2
Rev. 1.4
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table of Contents
System Overview.................................................................................................... 17
Absolute Maximum Ratings .................................................................................. 24
Global DC Electrical Characteristics .................................................................... 25
Pinout and Package Definitions............................................................................ 28
10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)........................................ 41
5.1. Analog Multiplexer ............................................................................................ 42
5.2. Temperature Sensor ......................................................................................... 43
5.3. Modes of Operation .......................................................................................... 45
5.3.1. Starting a Conversion............................................................................... 45
5.3.2. Tracking Modes........................................................................................ 46
5.3.3. Settling Time Requirements ..................................................................... 47
5.4. Programmable Window Detector ...................................................................... 52
5.4.1. Window Detector In Single-Ended Mode ................................................. 54
5.4.2. Window Detector In Differential Mode...................................................... 55
6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)....................................... 57
7. Comparators ........................................................................................................... 59
8. Voltage Regulator (REG0)...................................................................................... 69
8.1. Regulator Mode Selection................................................................................. 69
8.2. VBUS Detection ................................................................................................ 69
9. CIP-51 Microcontroller ........................................................................................... 73
9.1. Instruction Set ................................................................................................... 74
9.1.1. Instruction and CPU Timing ..................................................................... 74
9.1.2. MOVX Instruction and Program Memory ................................................. 75
9.2. Memory Organization........................................................................................ 79
9.2.1. Program Memory...................................................................................... 80
9.2.2. Data Memory............................................................................................ 81
9.2.3. General Purpose Registers ...................................................................... 81
9.2.4. Bit Addressable Locations........................................................................ 81
9.2.5. Stack ....................................................................................................... 81
9.2.6. Special Function Registers....................................................................... 82
9.2.7. Register Descriptions ............................................................................... 86
9.3. Interrupt Handler ............................................................................................... 88
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 88
9.3.2. External Interrupts .................................................................................... 88
9.3.3. Interrupt Priorities ..................................................................................... 89
9.3.4. Interrupt Latency ...................................................................................... 89
9.3.5. Interrupt Register Descriptions................................................................. 90
9.4. Power Management Modes .............................................................................. 97
9.4.1. Idle Mode.................................................................................................. 97
9.4.2. Stop Mode ................................................................................................ 97
10. Prefetch Engine ...................................................................................................... 99
11. Reset Sources....................................................................................................... 100
11.1.Power-On Reset ............................................................................................. 101
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
11.2.Power-Fail Reset / VDD Monitor .................................................................... 102
11.3.External Reset ................................................................................................ 103
11.4.Missing Clock Detector Reset ........................................................................ 103
11.5.Comparator0 Reset ........................................................................................ 103
11.6.PCA Watchdog Timer Reset .......................................................................... 103
11.7.Flash Error Reset ........................................................................................... 103
11.8.Software Reset ............................................................................................... 104
11.9.USB Reset...................................................................................................... 104
12. Flash Memory ....................................................................................................... 107
12.1.Programming The Flash Memory ................................................................... 107
12.1.1.Flash Lock and Key Functions ............................................................... 107
12.1.2.Flash Erase Procedure .......................................................................... 107
12.1.3.Flash Write Procedure ........................................................................... 108
12.2.Non-Volatile Data Storage.............................................................................. 109
12.3.Security Options ............................................................................................. 109
13. External Data Memory Interface and On-Chip XRAM........................................ 114
13.1.Accessing XRAM............................................................................................ 114
13.1.1.16-Bit MOVX Example ........................................................................... 114
13.1.2.8-Bit MOVX Example ............................................................................. 114
13.2.Accessing USB FIFO Space .......................................................................... 115
13.3.Configuring the External Memory Interface .................................................... 116
13.4.Port Configuration........................................................................................... 116
13.5.Multiplexed and Non-multiplexed Selection.................................................... 119
13.5.1.Multiplexed Configuration....................................................................... 119
13.5.2.Non-multiplexed Configuration............................................................... 120
13.6.Memory Mode Selection................................................................................. 120
13.6.1.Internal XRAM Only ............................................................................... 121
13.6.2.Split Mode without Bank Select.............................................................. 121
13.6.3.Split Mode with Bank Select................................................................... 122
13.6.4.External Only.......................................................................................... 122
13.7.Timing .......................................................................................................... 122
13.7.1.Non-multiplexed Mode ........................................................................... 124
13.7.2.Multiplexed Mode ................................................................................... 127
14. Oscillators ............................................................................................................. 131
14.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 132
14.1.1.Internal H-F Oscillator Suspend Mode ................................................... 132
14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 133
14.2.1.Calibrating the Internal L-F Oscillator..................................................... 133
14.3.External Oscillator Drive Circuit...................................................................... 135
14.3.1.Clocking Timers Directly Through the External Oscillator...................... 135
14.3.2.External Crystal Example....................................................................... 135
14.3.3.External RC Example............................................................................. 136
14.3.4.External Capacitor Example................................................................... 136
14.4.4x Clock Multiplier .......................................................................................... 138
14.5.System and USB Clock Selection .................................................................. 139
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
14.5.1.System Clock Selection ......................................................................... 139
14.5.2.USB Clock Selection .............................................................................. 139
15. Port Input/Output.................................................................................................. 142
15.1.Priority Crossbar Decoder .............................................................................. 144
15.2.Port I/O Initialization ....................................................................................... 147
15.3.General Purpose Port I/O ............................................................................... 150
16. Universal Serial Bus Controller (USB0).............................................................. 159
16.1.Endpoint Addressing ...................................................................................... 160
16.2.USB Transceiver ............................................................................................ 160
16.3.USB Register Access ..................................................................................... 162
16.4.USB Clock Configuration................................................................................ 166
16.5.FIFO Management ......................................................................................... 167
16.5.1.FIFO Split Mode ..................................................................................... 167
16.5.2.FIFO Double Buffering ........................................................................... 168
16.5.3.FIFO Access .......................................................................................... 168
16.6.Function Addressing....................................................................................... 169
16.7.Function Configuration and Control................................................................ 169
16.8.Interrupts ........................................................................................................ 172
16.9.The Serial Interface Engine ............................................................................ 176
16.10.Endpoint0 ..................................................................................................... 176
16.10.1.Endpoint0 SETUP Transactions .......................................................... 177
16.10.2.Endpoint0 IN Transactions................................................................... 177
16.10.3.Endpoint0 OUT Transactions............................................................... 178
16.11.Configuring Endpoints1-3 ............................................................................. 180
16.12.Controlling Endpoints1-3 IN.......................................................................... 180
16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 180
16.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 181
16.13.Controlling Endpoints1-3 OUT...................................................................... 183
16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 183
16.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 184
17. SMBus ................................................................................................................... 188
17.1.Supporting Documents ................................................................................... 189
17.2.SMBus Configuration...................................................................................... 189
17.3.SMBus Operation ........................................................................................... 189
17.3.1.Arbitration............................................................................................... 190
17.3.2.Clock Low Extension.............................................................................. 191
17.3.3.SCL Low Timeout................................................................................... 191
17.3.4.SCL High (SMBus Free) Timeout .......................................................... 191
17.4.Using the SMBus............................................................................................ 191
17.4.1.SMBus Configuration Register............................................................... 192
17.4.2.SMB0CN Control Register ..................................................................... 195
17.4.3.Data Register ......................................................................................... 198
17.5.SMBus Transfer Modes.................................................................................. 198
17.5.1.Master Transmitter Mode ....................................................................... 198
17.5.2.Master Receiver Mode ........................................................................... 200
Rev. 1.3
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