• Supports numerous SerDes Transmit Voltage Margin
settings
– Unused SerDes are disabled
◆
Testability and Debug Features
– Per port link up and activity status outputs available on I/O
expander outputs
– Built in SerDes 8-bit and 10-bit pseudo-random bit stream
(PRBS) generators
– Numerous SerDes test modes, including a PRBS Master
Loopback mode for in-system link testing
– Ability to read and write any internal register via SMBus and
JTAG interfaces, including SerDes internal controls
– Per port statistics and performance counters, as well as propri-
etary link status registers
◆
General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Option A Package: 19mm x 19mm 324-ball Flip Chip BGA
with 1mm ball spacing
◆
Option B Package: 27mm x 27mm 676-ball Flip Chip BGA
with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES24T3G2
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 24 integrated serial lanes. Each lane provides 5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base Specification, Revision 2.0, including operation in 5 Gbps, 2.5
Gbps, and mixed 5 Gbps / 2.5Gbps modes.
The PES24T3G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
–
–
–
–
Revision 2.0. The PES24T3G2 can operate either as a store and
forward or cut-through switch and is designed to switch memory and I/O
transactions. It supports eight Traffic Classes (TCs) and one Virtual
Channel (VC) with sophisticated resource management to enable effi-
cient switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
Processor
Processor
North
Bridge
Memory
Memory
Memory
Memory
x8
PES24T3G2
x8
PCI Express
Slot
x8
I/O Dual
10GbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
SMBus Interface
The PES24T3G2 contains two SMBus interfaces. The slave inter-
face provides full access to the configuration registers in the
PES24T3G2, allowing every configuration register in the device to be
read or written by an external agent. The master interface allows the
default configuration register values of the PES24T3G2 to be over-
ridden following a reset with values programmed in an external serial
EEPROM. The master interface is also used by an external Hot-Plug I/O
expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be config-
ured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Note:
MSMBADDR and SSMBADDR address pins are not
available in the 19mm package. The MSMBADDR address is
hardwired to 0x50, and the SSMBADDR address is hardwired
to 0x77.
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*Notice: The information in this document is subject to change without notice
May 7, 2008
IDT 89HPES24T3G2 Data Sheet
Bit
1
2
3
4
5
6
7
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment for 27x27mm Package
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES24T3G2 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES24T3G2 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES24T3G2 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES24T3G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
Processor
SMBus
Master
Other
SMBus
Devices
Processor
SMBus
Master
Other
SMBus
Devices
PES24T3G2
Serial
EEPROM
...
PES24T3G2
...
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES24T3G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24T3G2
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES24T3G2 generates an SMBus transaction to the I/O expander with the
new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN
input pin (alternate function of GPIO) of the PES24T3G2. In response to an I/O expander interrupt, the PES24T3G2 generates an SMBus transaction
to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24T3G2 provides General Purpose Input/Output (GPIO) pins (7 pins in the 19mm package and 11 pins in the 27mm package) that may be
used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Many
GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configura-
tion EEPROM.
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May 7, 2008
IDT 89HPES24T3G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24T3G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note:
In the PES24T3G2, the two downstream ports are labeled port 2 and port 4.
Signal
PE0RP[7:0]
PE0RN[7:0]
PE0TP[7:0]
PE0TN[7:0]
PE2RP[7:0]
PE2RN[7:0]
PE2TP[7:0]
PE2TN[7:0]
PE4RP[7:0]
PE4RN[7:0]
PE4TP[7:0]
PE4TN[7:0]
PEREFCLKP
PEREFCLKN
Type
I
O
I
O
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 4.
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select.
This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Table 2 PCI Express Interface Pins
REFCLKM
1
I
1.
REFCLKM is not available in the 19mm package and frequency is set at 100MHz.
Signal
MSMBADDR[4:1]
1
MSMBCLK
MSMBDAT
SSMBADDR[5,3:1]
2
SSMBCLK
Type
I
I/O
I/O
I
I/O
Name/Description
Master SMBus Address.
These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus.
Slave SMBus Address.
These pins determine the SMBus address to
which the slave SMBus interface responds.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Table 3 SMBus Interface Pins (Part 1 of 2)
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May 7, 2008
IDT 89HPES24T3G2 Data Sheet
Signal
SSMBDAT
Type
I/O
Name/Description
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins (Part 2 of 2)
1.
MSMBADDR pins are not available in the 19mm package. Address hardwired to 0x50.
2.
SSMBADDR pins are not available in the 19mm package. Address hardwired to 0x77.
Signal
GPIO[0]
Type
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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