2211D225M0000VCK datasheet, PDF

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2211D225M0000VCK: DescriptionSine Output Oscillator; CategoryPassive components oscillator; File Size953KB，26 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/

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2211D225M0000VCK Overview

Sine Output Oscillator

2211D225M0000VCK Parametric

Parameter Name	Attribute value
Objectid	7107087384
Reach Compliance Code	compliant
Oscillator type	SINE

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REV

DESCRIPTION

CO-

DATE

PREP

DF/SM

APPD

Specification, Hybrid TCXO

MOUNT HOLLY SPRINGS, PA 17065

THE RECORD OF APPROVAL FOR THIS

DOCUMENT IS MAINTAINED ELECTRONICALLY

WITHIN THE ERP SYSTEM

CODE IDENT NO

Hi-Rel Standard

SIZE

DWG. NO.

REV

00136

DOC200103

UNSPECIFIED TOLERANCES: N/A

SHEET 1 0F 26

1.1

SCOPE

General. This specification defines the design, assembly and functional evaluation of high

reliability, hybrid TCXOs produced by Vectron International. Devices delivered to this

specification represent the standardized Parts, Materials and Processes (PMP) Program

developed, implemented and certified for advanced applications and extended environments.

Applications Overview. The designs represented by these products were primarily developed

for the MIL-Aerospace community. The lesser Design Pedigrees and Screening Options

imbedded within DOC200103 bridge the gap between Space and COTS hardware by providing

custom hardware with measures of mechanical, assembly and reliability assurance needed for

Military, Ruggedized COTS or Commercial environments.

1.2

2.1

APPLICABLE DOCUMENTS

Specifications and Standards. The following specifications and standards form a part of this

document to the extent specified herein. The issue currently in effect on the date of quotation

will be the product baseline, unless otherwise specified. In the event of conflict between the

texts of any references cited herein, the text of this document shall take precedence.

Military

MIL-PRF-55310

MIL-PRF-38534

Standards

MIL-STD-202

MIL-STD-883

Oscillators, Crystal Controlled, General Specification For

Hybrid Microcircuits, General Specification For

Test Method Standard, Electronic and Electrical Component Parts

Test Methods and Procedures for Microelectronics

Vectron International

QSP-90100

VL-65339

DOC203982

QSP-91502

3.1

Quality Systems Manual, Vectron International

Identification Common Documents, Materials and Processes, Hi-Rel XO

DPA Specification

Procedure for Electrostatic Discharge Precautions

GENERAL REQUIREMENTS

Classification. All devices delivered to this specification are of hybrid technology conforming

to Type 3, Class 2 of MIL-PRF-55310. Devices carry a Class 1C ESDS classification per

MIL-PRF-38534 and are marked with a single equilateral triangle at pin 1 per MIL-PRF-

55310.

Item Identification. External packaging choices are either metal flatpacks or DDIP with either

Sinewave or CMOS logic output. Unique Model Number Series’ are utilized to identify device

package configurations and output waveform as listed in Table 1.

UNSPECIFIED TOLERANCES

3.2

SIZE

CODE IDENT NO.

DWG NO.

REV.

SHEET

00136

N/A

DOC200103

3.3

Absolute Maximum Ratings.

a. Supply Voltage Range (V

b. Storage Temperature Range (T

STG

c. Junction Temperature (T

d. Lead Temperature (soldering, 10 seconds):

-0.5Vdc to +7.0Vdc (+5V CMOS)

-0.5Vdc to +5.0Vdc (+3.3V CMOS)

Contact factory for sinewave output

-65°C to +125°C

+150C

+300°C

3.4

3.4.1

Design, Parts, Materials and Processes, Assembly, Inspection and Test.

Design. The ruggedized designs implemented for these devices are proven in military and

space applications under extreme environments. All designs utilize a 4-point crystal mount.

For radiation characteristics, see paragraph 4.1.3. For all Class S and Class B products,

components meet the Element Evaluation requirements of MIL-PRF-55310, Appendix B. If

Design Pedigree Code “E” is chosen, Enhanced Element Evaluation per Appendix A herein

will be performed.

3.4.1.1 Design and Configuration Stability. Barring changes to improve performance by reselecting

passive chip component values to offset component tolerances, there will not be fundamental

changes to the design or assembly or parts, materials and processes after first product delivery

of that item without written approval from the procuring activity.

3.4.1.2 Environmental Integrity. Designs have passed the environmental qualification levels of MIL-

PRF-55310. These designs have also passed extended dynamic levels of at least:

a. Sine Vibration: MIL-STD-202, Method 204, Condition G (30g pk.)

b. Random Vibration: MIL-STD-202, Method 214, Condition II-J (43.92g rms, three

minute duration in each of three mutually perpendicular directions)

c. Mechanical Shock: MIL-STD-202, Method 213, Condition F (1500g, 0.5ms)

3.4.2

Prohibited Parts, Materials and Processes. The items listed are prohibited for use in high

reliability devices produced to this specification.

a. Gold metallization of package elements without a barrier metal.

b. Zinc chromate as a finish.

c. Cadmium, zinc, or pure tin external or internal to the device.

d. Plastic encapsulated semiconductor devices.

e. Ultrasonically cleaned electronic parts.

f. Heterojunction Bipolar Transistor (HBT) technology.

Assembly. Manufacturing utilizes standardized procedures, processes and verification

methods to produce MIL-PRF-55310 Class S / MIL-PRF-38534 Class K equivalent devices.

MIL-PRF-38534 Group B Option 1 in-line inspection is included on levels E and R per

paragraph 7.1 to further verify lot pedigree. Traceability of all components and production lots

are in accordance with MIL-PRF-38534, as a minimum. Tabulated records are provided as a

part of the deliverable data package. Devices are handled in accordance with Vectron

document QSP-91502 (Procedure for Electrostatic Discharge Precautions).

UNSPECIFIED TOLERANCES

3.4.3

SIZE

CODE IDENT NO.

DWG NO.

REV.

SHEET

00136

N/A

DOC200103

3.4.4

Inspection. The inspection requirements of MIL-PRF-55310 apply to all devices delivered to

this document. Inspection conditions and standards are documented in accordance with the

Quality Assurance, ISO-9001 derived system of QSP-90100.

Test. The Screening test matrix of Table 4 is tailored for selectable-combination testing to

eliminate costs associated with the development/maintenance of device-specific documentation

packages while maintaining performance integrity.

Marking. Device marking shall be in accordance with the requirements of MIL-PRF-55310.

Ruggedized COTS Design Implementation. Design Pedigree “D” devices (see ¶ 5.2) use the

same robust designs as the other device pedigrees. They do not include the provisions of

traceability or the Class-qualified componentry noted in paragraphs 3.4.3 and 4.1.

DETAIL REQUIREMENTS

Components

Crystals. Cultured quartz crystal resonators are used to provide the selected frequency for the

devices. Premium Q swept quartz is standard for all Class S level products because of its

superior radiation tolerance. For Class B level products, swept quartz is optional, as required

by the customer. In accordance with MIL-PRF-55310, the manufacturer has a documented

crystal evaluation program.

Passive Components. Where possible, for Design Pedigrees ‘E’ & ‘R’, Established Reliability

(ER) failure level R and S passive components are employed. Otherwise, all components

comply with the Element Evaluation requirements of MIL-PRF-38534 or Enhanced Element

Evaluation as specified in Appendix A herein. When used, inductors may be open construction

and may use up to 47 gauge wire.

Class S Microcircuits. Microcircuits are procured from wafer lots that have passed MIL-PRF-

38534 Class K Lot Acceptance Tests for Class S devices. Although radiation testing is not

performed at the oscillator level, Design Pedigree Codes E and R versions of this TCXO are

acceptable for use in environments of up to 100krad (Si) total dose as a result of wafer lot

specific RLAT or by analysis of the individual components. Sinewave devices are assembled

with all bipolar semiconductors.

ACMOS devices are assembled with all bipolar

semiconductors with the exception of the ACMOS chip used to provide the CMOS output. An

ACMOS die from a radiation tested and certified wafer lot will be provided for all Class S

versions of this TCXO. This microcircuit is certified for 100krads (Si) total ionizing dose

(TID), RHA level R (2X minimum margin). NSC, as the 54ACT designer, rates the SET LET

at > 40MeV and SEL at >120MeV for the FACT™ family (AN-932). Vectron has conducted

additional SEE testing in 2008 to verify this performance since our lot wafer testing does not

include these parameters and determinations.

A copy of the parts list and materials can be provided for customer review upon request.

UNSPECIFIED TOLERANCES

3.4.5

3.4.6

3.4.7

4.1

4.1.1

4.1.2

4.1.3

SIZE

CODE IDENT NO.

DWG NO.

REV.

SHEET

00136

N/A

DOC200103

4.1.3.1 Class B Microcircuits. When specified, microcircuits assembled into Pedigree Codes B and C

devices (¶ 5.2a) are procured from wafer lots that have passed MIL-PRF-55310 element

evaluations for Class B devices.

4.1.4

Packages. Packages are procured that meet the construction, lead materials and finishes as

specified in MIL-PRF-55310. All leads are Kovar with gold plating over a nickel underplate.

Package lots are evaluated in accordance with the requirements of MIL-PRF-38534 as

applicable.

Traceability and Homogeneity. All design pedigrees except option D have active device lots

that are homogenous and traceable to the manufacturer’s individual wafer. Swept Quartz

Crystals are traceable to the quartz bar and the processing details of the autoclave lot, as

applicable. All other elements and materials are traceable to their manufacturing lots.

Manufacturing lot and date code information shall be recorded, by TCXO serial number, of

every component and all materials used in the manufacture of that TCXO. All semiconductors

used in the manufacture of a given production lot of TCXOs shall be from the same wafer and

have the same manufacturing lot date code. A production lot, as defined by Vectron, is all

oscillators that have been kitted and assembled as a single group. After the initial kitting and

assembly, this production lot may be divided into multiple sublots to facilitate alignment and

test capacity and may be sealed at multiple times within a 13 week window.

Mechanical.

Package Outline. Table 1 links each Hi-Rel Standard Model Number of this specification to a

corresponding package style. Mechanical Outline information of each package style is found

in the referenced Figure.

Thermal Characteristics. Because these TCXOs are multichip hybrid designs, the actual

any one given semiconductor die will vary, but the combined average for all active devices

results in a

of approximately 40°C/W. The typical die temperature rise at any one given

semiconductor is 2°C to 4°C. With the oscillator operating at +125°C, the average junction

temperature is approximately +129°C and under no circumstance will it ever exceed the

maximum manufacturer’s rated junction temperature.

Electrical.

Input Power. CMOS devices are designed for 3.3 ±5% or 5.0 volt ±5% DC operation.

Sinewave devices are designed for 3.3, 5.0, 12.0 or 15.0 volt dc operation with ±5% tolerance.

Temperature Range. Operating range is IAW the chosen temperature stability code.

Frequency Tolerance. Temperature stability includes initial accuracy at +25°C (with EFC),

load ±10% and supply ±5%.

4.1.5

4.2

4.2.1

4.2.2

4.3

4.3.1

4.3.2

4.3.3

SIZE

CODE IDENT NO.

UNSPECIFIED TOLERANCES

DWG NO.

REV.

SHEET

00136

N/A

DOC200103

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