TRU050-GCCFB-25M2480000 datasheet, PDF

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TRU050-GCCFB-25M2480000: DescriptionPhase Locked Loop, CDSO16; CategoryAnalog mixed-signal IC The signal circuit; File Size427KB，14 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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TRU050-GCCFB-25M2480000 Overview

Phase Locked Loop, CDSO16

TRU050-GCCFB-25M2480000 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	4017722104
package instruction	SMD-16
Reach Compliance Code	compliant
Country Of Origin	USA
YTEOL	6.8
Other features	SEATED HEIGHT CALCULATED
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CDSO-G16
JESD-609 code	e4
length	20.32 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Maximum seat height	5.58 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	GOLD OVER NICKEL
Terminal form	GULL WING
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	7.88 mm

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TRU050

Complete VCXO based Phase-Locked Loop

Features

•

Output Frequencies to 65.536 MHz

•

5.0 V or 3.3Vdc Operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS Outputs

•

0/70° or –40/85° Temperature Range

•

Ceramic SMD Package

•

RoHS/Lead Free Compliant Versions

The TRU050, VCXO based PLL

Description

The VI TRU050 is a user-configurable crystal-based

PLL integrated circuit. It includes a digital phase

detector, op-amp, VCXO and additional integrated

functions for use in digital synchronization

applications. Loop filter software is available as well

SPICE models for circuit simulation.

Applications

•

Frequency Translation

•

Clock Smoothing

•

NRZ Clock Recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low Jitter PLL’s

Figure 1. TRU050 Block Diagram

Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916

Page 1 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev:

4/12/2016

TRU050, VCXO Based PLL

TRU050 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4 volts.

DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which have about a

50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these outputs. CLKIN

and DATAIN and are protected by ESD diodes and should not exceed the power supply voltage or ground by

more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to produce

a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a block

diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer does not

have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN will be centered

in the middle of the DATAIN signal, see figure 6.

The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for 3.3

volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design for NRZ

signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces signficant

ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency applications

such as 8kHz frequency translation, see figures 8 and 9.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC gain, so

under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will not vary

signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will vary according

to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 7)

Clock In

(pin 9)

30 kΩ

20 kΩ

PHO

(pin 6)

Gain = 5 V / 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Unit 102, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev:

4/12/2016

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