74HC273DB-T datasheet, PDF - EEWORLD Datasheet

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74HC273DB-T: DescriptionTrigger octal D-type; Categorylogic logic; File Size153KB，26 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74HC273DB-T Overview

Trigger octal D-type

74HC273DB-T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	20
Reach Compliance Code	unknow
series	HC/UH
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	7.2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	225 ns
Certification status	Not Qualified
Maximum seat height	2 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	5.3 mm
minfmax	24 MHz

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74HC273; 74HCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Rev. 03 — 24 January 2006

Product data sheet

1. General description

The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL).

The 74HC273; 74HCT273 has eight edge-triggered, D-type ﬂip-ﬂops with individual

D inputs and Q outputs. The common clock (pin CP) and master reset (pin MR) inputs

load and reset (clear) all ﬂip-ﬂops simultaneously. The state of each D input, one set-up

time before the LOW-to-HIGH clock transition, is transferred to the corresponding output

(Qn) of the ﬂip-ﬂop.

All outputs will be forced LOW independently of clock or data inputs by a LOW voltage

level on the MR input.

The device is useful for applications where the true output only is required and the clock

and master reset are common to all storage elements.

2. Features

Ideal buffer for MOS microprocessor or memory

Common clock and master reset

Eight positive edge-triggered D-type ﬂip-ﬂops

Complies with JEDEC standard no. 7A

ESD protection:

HBM EIA/JESD22-A114-C exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Quick reference data

Table 1:

Quick reference data

GND = 0 V; T

amb

= 25

C; t

= t

= 6 ns.

Symbol Parameter

74HC273

PHL

PLH

PHL

max

propagation delay CP to Qn

HIGH-to-LOW propagation

delay MR to Qn

maximum input clock

frequency

= 5 V; C

= 15 pF

= 5 V; C

= 15 pF

= 5 V; C

= 15 pF

MHz

Conditions

Min

Typ

Max

Unit

74HC273DB-T Related Products

	74HC273DB-T	5962-01-269-2702	74HC273BQ	74HCT273BQ
Description	Trigger octal D-type	IC IC,FLIP-FLOP,OCTAL,D TYPE,HCT-CMOS,DIP,20PIN,PLASTIC, FF/Latch	IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20, FF/Latch	IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PQCC20, 2.50 X 4.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT-764-1, DHVQFN-20, FF/Latch
Is it Rohs certified?	conform to	conform to	conform to	conform to
package instruction	SSOP,	DIP, DIP20,.3	HVQCCN, LCC20/24,.14X.18,20	HVQCCN, LCC20/24,.14X.18,20
Reach Compliance Code	unknow	compli	compliant	compliant
JESD-30 code	R-PDSO-G20	R-PDIP-T20	R-PQCC-N20	R-PQCC-N20
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of functions	1	8	1	1
Number of terminals	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	DIP	HVQCCN	HVQCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	IN-LINE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	GULL WING	THROUGH-HOLE	NO LEAD	NO LEAD
Terminal pitch	0.65 mm	2.54 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	QUAD	QUAD
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
Maker	NXP	-	NXP	NXP
Parts packaging code	SSOP	-	QFN	QFN
Contacts	20	-	20	20
series	HC/UH	-	HC/UH	HCT
JESD-609 code	e4	-	e4	e4
length	7.2 mm	-	4.5 mm	4.5 mm
Humidity sensitivity level	1	-	1	1
Number of digits	8	-	8	8
Output polarity	TRUE	-	TRUE	TRUE
Peak Reflow Temperature (Celsius)	260	-	260	260
propagation delay (tpd)	225 ns	-	225 ns	45 ns
Maximum seat height	2 mm	-	1 mm	1 mm
Maximum supply voltage (Vsup)	6 V	-	6 V	5.5 V
Minimum supply voltage (Vsup)	2 V	-	2 V	4.5 V
Terminal surface	NICKEL PALLADIUM GOLD	-	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Maximum time at peak reflow temperature	30	-	30	30
width	5.3 mm	-	2.5 mm	2.5 mm
minfmax	24 MHz	-	24 MHz	20 MHz
MaximumI(ol)	-	0.004 A	0.004 A	0.004 A
Encapsulate equivalent code	-	DIP20,.3	LCC20/24,.14X.18,20	LCC20/24,.14X.18,20
power supply	-	5 V	2/6 V	5 V

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