IS71V16F32GST04-7070BI datasheet, PDF

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IS71V16F32GST04-7070BI: DescriptionMemory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA59, 7 X 9 MM, 0.80 MM PITCH, FBGA-59; Categorystorage storage; File Size188KB，49 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS71V16F32GST04-7070BI Overview

Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA59, 7 X 9 MM, 0.80 MM PITCH, FBGA-59

IS71V16F32GST04-7070BI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	7 X 9 MM, 0.80 MM PITCH, FBGA-59
Contacts	59
Reach Compliance Code	compliant
Maximum access time	70 ns
Other features	SRAM IS ORGANISED AS 256K X 16
JESD-30 code	R-PBGA-B59
JESD-609 code	e0
length	9 mm
memory density	33554432 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Mixed memory types	FLASH+SRAM
Number of functions	1
Number of terminals	59
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA59,8X10,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.000005 A
Maximum slew rate	0.043 mA
Maximum supply voltage (Vsup)	3.3 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm
Base Number Matches	1

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IS71V16F32GST04

IS71V16F32GSB04

3.0 Volt-Only Flash & SRAM COMBO with

Stacked Multi-Chip Package (MCP)

— 32 Mbit Simultaneous Operation Flash

Memory (x16) and 4 Mbit Static RAM (x16)

MCP FEATURES

•

Power supply voltage 2.7V to 3.3V

•

High performance:

Flash: 70ns maximum access time

SRAM: 70ns maximum access time

ISSI

•

Top or Bottom Boot

•

Hidden ROM Region:

256 byte with a Factory-serialized secure electronic

serial number (ESN), which is accessible through a

command sequence

PRELIMINARY INFORMATION

DECEMBER 2002

•

Packages: 59-ball BGA or 56-ball BGA

•

Operating Temperature: -30C to +85C

•

Data Polling and Toggle Bit:

Allow for detection of program or erase cycle comple-

tion

FLASH FEATURES

•

Power Dissipation:

Read Current at 1 Mhz: 4 mA maximum

Read Current at 5 Mhz:18 mA maximum

Sleep Mode: 5

µA

maximum

• User Configurable Banks

- Bank A : 4 Mbit (8KB x 8 and 64KB x 7)

- Bank B : 12 Mbit (64KB x 24)

- Bank C : 12 Mbit (64KB x 24)

- Bank D : 4 Mbit (64KB x 8 )

User chooses two virtual banks from a combination

of four physical banks

•

Simultaneous R/W Operations (dual virtual bank):

Zero latency between read and write operations; Data

can be programmed or erased in one bank while data

is simultaneously being read from the other bank

•

Ready-Busy output (RY/BY)

Detection of program or erase cycle completion

•

Over 100,000 write/erase cycles

•

Low supply voltage (Vccf

≤

2.5V) inhibits writes

•

WP/ACC

input pin:

If V

, allows partial protection of boot sectors

If V

, allows removal of boot sector protection

If Vacc, program time is improved

SRAM FEATURES (4 Mb density)

•

Power Dissipation:

Operating: 40 mA maximum

Standby: 10 µA maximum

Chip Selects:

CE1s,

CE2s

Power down feature using

CE1s,

or CE2s

Data retention supply voltage: 1.5 to 3.3 volt

Byte data control:

LBs

(DQ0–DQ7),

UBs

(DQ8–DQ15)

•

Low-Power Mode:

A period of no activity causes flash to enter a

low-power state

•

Erase Suspend/Resume:

Suspends of erase activity to allow a read in the

same bank

•

Sector Erase Architecture:

8 sectors of 4K words each and 63 sectors of 32K words

each in Word mode. Any combination of sectors, or

the entire flash can be simultaneously erased

•

Erase Algorithms:

Automatically preprograms/erases the flash memory

entirely, or by sector

•

Program Algorithms:

Automatically writes and verifies data at specified

address

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. 00C

12/05/02

IS71V16F32GST04-7070BI Related Products

	IS71V16F32GST04-7070BI	IS71V16F32GSB04-7070BI	IS71V16F32GSB04-7070MI
Description	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA59, 7 X 9 MM, 0.80 MM PITCH, FBGA-59	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA59, 7 X 9 MM, 0.80 MM PITCH, FBGA-59	Memory Circuit, Flash+SRAM, 2MX16, CMOS, PBGA56, 7 X 9 MM, 0.80 MM PITCH, FBGA-56
Is it lead-free?	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA	BGA	BGA
package instruction	7 X 9 MM, 0.80 MM PITCH, FBGA-59	7 X 9 MM, 0.80 MM PITCH, FBGA-59	7 X 9 MM, 0.80 MM PITCH, FBGA-56
Contacts	59	59	56
Reach Compliance Code	compliant	compliant	compliant
Maximum access time	70 ns	70 ns	70 ns
Other features	SRAM IS ORGANISED AS 256K X 16	SRAM IS ORGANISED AS 256K X 16	SRAM IS ORGANISED AS 256K X 16
JESD-30 code	R-PBGA-B59	R-PBGA-B59	R-PBGA-B56
JESD-609 code	e0	e0	e0
length	9 mm	9 mm	9 mm
memory density	33554432 bit	33554432 bit	33554432 bit
Memory IC Type	MEMORY CIRCUIT	MEMORY CIRCUIT	MEMORY CIRCUIT
memory width	16	16	16
Mixed memory types	FLASH+SRAM	FLASH+SRAM	FLASH+SRAM
Number of functions	1	1	1
Number of terminals	59	59	56
word count	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-30 °C	-30 °C	-30 °C
organize	2MX16	2MX16	2MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA59,8X10,32	BGA59,8X10,32	BGA56,8X8,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3 V	3 V	3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm
Maximum standby current	0.000005 A	0.000005 A	0.000005 A
Maximum slew rate	0.043 mA	0.043 mA	0.043 mA
Maximum supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	7 mm	7 mm	7 mm
Base Number Matches	1	1	1

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