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DM74LS75

Description
LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16
Categorysemiconductor    logic   
File Size45KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

DM74LS75 Overview

LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16

DM74LS75 Parametric

Parameter NameAttribute value
Number of functions2
Number of terminals16
Minimum operating temperature0.0 Cel
Maximum operating temperature70 Cel
Rated supply voltage5
Minimum supply/operating voltage4.75 V
Maximum supply/operating voltage5.25 V
Processing package descriptionPLASTIC, DIP-16
stateTransferred
Logic IC typeD LATCH
sub_categoryFF/Latches
seriesLS
jesd_30_codeR-PDIP-T16
load_capacitance__cl_15 pF
max_i_ol_0.0080 Am
Number of digits2
Output polarityCOMPLEMENTARY
Packaging MaterialsPLASTIC/EPOXY
ckage_codeDIP
ckage_equivalence_codeDIP16,.3
packaging shapeRECTANGULAR
Package SizeIN-LINE
wer_supplies__v_5
wer_supply_current_max__icc_12 mA
._delay_nom_su30 ns
propagation delay TPD30 ns
qualification_statusCOMMERCIAL
seated_height_max5.08 mm
surface mountNO
CraftsmanshipTTL
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
Terminal locationDUAL
length21.76 mm
width7.62 mm
DM74LS75 Quad Latch
August 1986
Revised March 2000
DM74LS75
Quad Latch
General Description
These latches are ideally suited for use as temporary stor-
age for binary information between processing units and
input/output or indicator units. Information present at a data
(D) input is transferred to the Q output when the enable is
HIGH, and the Q output will follow the data input as long as
the enable remains HIGH. When the enable goes LOW, the
information (that was present at the data input at the time
the transition occurred) is retained at the Q output until the
enable is permitted to go HIGH.
These latches feature complementary Q and Q outputs
from a 4-bit latch, and are available in 16-pin packages.
Ordering Code:
Order Number
DM74LS75M
DM74LS75N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
(Each Latch)
Connection Diagram
Function Table
Inputs
D
L
H
X
(Each Latch)
Outputs
Q
L
H
Q
0
Q
H
L
Q
0
Enable
H
H
L
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
Q
0
=
The Level of Q Before the HIGH-to-LOW Transition of ENABLE
© 2000 Fairchild Semiconductor Corporation
DS006374
www.fairchildsemi.com

DM74LS75 Related Products

DM74LS75 74LS75 DM74LS75M DM74LS75N
Description LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16
Number of functions 2 2 2 2
Number of terminals 16 16 16 16
Maximum operating temperature 70 Cel 70 Cel 70 °C 70 °C
series LS LS LS LS
Number of digits 2 2 2 2
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
surface mount NO NO YES NO
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE THROUGH-HOLE GULL WING THROUGH-HOLE
Terminal location DUAL DUAL DUAL DUAL
length 21.76 mm 21.76 mm 9.9 mm 19.305 mm
width 7.62 mm 7.62 mm 3.9 mm 7.62 mm
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