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DM74LS75N

Description
LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16
Categorylogic    logic   
File Size45KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS75N Overview

LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16

DM74LS75N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instruction0.300 INCH, PLASTIC, MS-001, DIP-16
Contacts16
Reach Compliance Codeunknown
seriesLS
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeD LATCH
MaximumI(ol)0.008 A
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)12 mA
Prop。Delay @ Nom-Sup30 ns
propagation delay (tpd)30 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeHIGH LEVEL
width7.62 mm
Base Number Matches1
DM74LS75 Quad Latch
August 1986
Revised March 2000
DM74LS75
Quad Latch
General Description
These latches are ideally suited for use as temporary stor-
age for binary information between processing units and
input/output or indicator units. Information present at a data
(D) input is transferred to the Q output when the enable is
HIGH, and the Q output will follow the data input as long as
the enable remains HIGH. When the enable goes LOW, the
information (that was present at the data input at the time
the transition occurred) is retained at the Q output until the
enable is permitted to go HIGH.
These latches feature complementary Q and Q outputs
from a 4-bit latch, and are available in 16-pin packages.
Ordering Code:
Order Number
DM74LS75M
DM74LS75N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
(Each Latch)
Connection Diagram
Function Table
Inputs
D
L
H
X
(Each Latch)
Outputs
Q
L
H
Q
0
Q
H
L
Q
0
Enable
H
H
L
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
Q
0
=
The Level of Q Before the HIGH-to-LOW Transition of ENABLE
© 2000 Fairchild Semiconductor Corporation
DS006374
www.fairchildsemi.com

DM74LS75N Related Products

DM74LS75N 74LS75 DM74LS75 DM74LS75M
Description LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16 LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16
series LS LS LS LS
length 19.305 mm 21.76 mm 21.76 mm 9.9 mm
Number of digits 2 2 2 2
Number of functions 2 2 2 2
Number of terminals 16 16 16 16
Maximum operating temperature 70 °C 70 Cel 70 Cel 70 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
surface mount NO NO NO YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE GULL WING
Terminal location DUAL DUAL DUAL DUAL
width 7.62 mm 7.62 mm 7.62 mm 3.9 mm
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