DM74S373N datasheet, PDF - EEWORLD Datasheet

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DM74S373N: Description3-STATE Octal D-Type Transparent Latches; Categorylogic logic; File Size71KB，7 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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DM74S373N Overview

3-STATE Octal D-Type Transparent Latches

DM74S373N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	DIP
package instruction	DIP, DIP20,.3
Contacts	20
Reach Compliance Code	unknow
series	S
JESD-30 code	R-PDIP-T20
JESD-609 code	e0
length	26.075 mm
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.02 A
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	190 mA
Prop。Delay @ Nom-Su	16 ns
propagation delay (tpd)	16 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

August 1986

Revised May 2000

DM74S373 • DM74S374

3-STATE Octal D-Type Transparent Latches

and Edge-Triggered Flip-Flops

General Description

These 8-bit registers feature totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high-logic-level drive provide these registers with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without need for inter-

face or pull-up components. They are particularly attractive

for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

The eight latches of the DM74S373 are transparent D-type

latches meaning that while the enable (G) is HIGH the Q

outputs will follow the data (D) inputs. When the enable is

taken LOW the output will be latched at the level of the

data that was set up.

The eight flip-flops of the DM74S374 are edge-triggered D-

type flip-flops. On the positive transition of the clock, the Q

outputs will be set to the logic states that were set up at the

D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines

simplify system design as ac and dc noise rejection is

improved by typically 400 mV due to the input hysteresis. A

buffered output control input can be used to place the eight

outputs in either a normal logic state (HIGH or LOW logic

levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines signifi-

cantly.

The output control does not affect the internal operation of

the latches or flip-flops. That is, the old data can be

retained or new data can be entered even while the outputs

are OFF.

Features

Choice of 8 latches or 8 D-type flip-flops in a single

package

3-STATE bus-driving outputs

Full parallel-access for loading

Buffered control inputs

P-N-P input reduce D-C loading on data lines

Ordering Code:

Order Number

DM74S373WM

DM74S373N

DM74S374WM

DM74S374N

Package Number

M20B

N20A

M20B

N20A

Package Description

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

DM74S373N

DM74S374N

DS006486

www.fairchildsemi.com

DM74S373N Related Products

	DM74S373N	DM74S374N	DM74S373	DM74S374WM	DM74S373WM
Description	3-STATE Octal D-Type Transparent Latches	3-STATE Octal D-Type Transparent Latches	3-STATE Octal D-Type Transparent Latches	3-STATE Octal D-Type Transparent Latches	3-STATE Octal D-Type Transparent Latches
Is it Rohs certified?	incompatible	incompatible	-	incompatible	incompatible
Maker	Fairchild	Fairchild	-	Fairchild	Fairchild
Parts packaging code	DIP	DIP	-	SOIC	SOIC
package instruction	DIP, DIP20,.3	DIP, DIP20,.3	-	0.300 INCH, MS-013, SOIC-20	SOP, SOP20,.4
Contacts	20	20	-	20	20
Reach Compliance Code	unknow	unknow	-	unknow	unknow
series	S	S	-	S	S
JESD-30 code	R-PDIP-T20	R-PDIP-T20	-	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e0	e0	-	e0	e0
length	26.075 mm	26.075 mm	-	12.8 mm	12.8 mm
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	-	BUS DRIVER	BUS DRIVER
MaximumI(ol)	0.02 A	0.02 A	-	0.02 A	0.02 A
Number of digits	8	8	-	8	8
Number of functions	1	1	-	1	1
Number of ports	2	2	-	2	2
Number of terminals	20	20	-	20	20
Maximum operating temperature	70 °C	70 °C	-	70 °C	70 °C
Output characteristics	3-STATE	3-STATE	-	3-STATE	3-STATE
Output polarity	TRUE	TRUE	-	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	-	SOP	SOP
Encapsulate equivalent code	DIP20,.3	DIP20,.3	-	SOP20,.4	SOP20,.4
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	-	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	-	5 V	5 V
Maximum supply current (ICC)	190 mA	160 mA	-	160 mA	190 mA
propagation delay (tpd)	16 ns	20 ns	-	20 ns	16 ns
Certification status	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm	-	2.65 mm	2.65 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	-	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	-	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	-	5 V	5 V
surface mount	NO	NO	-	YES	YES
technology	TTL	TTL	-	TTL	TTL
Temperature level	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	-	GULL WING	GULL WING
Terminal pitch	2.54 mm	2.54 mm	-	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	-	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	7.62 mm	-	7.5 mm	7.5 mm

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