Freescale Semiconductor
Data Sheet: Technical Data
An Energy Efficient Solution by Freescale
Document Number: MC9S08LL16
Rev. 7, 1/2013
MC9S08LL16 Series
Covers: MC9S08LL16 and
MC9S08LL8
Features
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 20-MHz CPU at 3.6V to 1.8V across temperature range
of -40°C to 85°C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Dual Array FLASH read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
FLASH contents
• Power-Saving Modes
– Two low power stop modes
– Reduced power wait mode
– Low power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents.
– Very low power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to real time
counter
– 6 usec typical wake up time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal
or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz
to 16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supports bus frequencies from 1MHz
to 10 MHz.
• System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1-kHz internal clock source or
bus clock
– Low-Voltage Warning with interrupt
– Low-Voltage Detection with reset or interrupt
– Illegal opcode and illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip
debug module)
64-LQFP
Case 840F
48-LQFP
Case 932
48-QFN
1314
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes. Eight deep FIFO for
storing change-of-flow addresses and event-only data. Debug
module supports both tag and force breakpoints
• Peripherals
–
LCD
— 4x28 or 8x24 LCD driver with internal charge pump
and option to provide an internally regulated LCD reference
that can be trimmed for contrast control.
–
ADC
— 8-channel, 12-bit resolution; 2.5
μs
conversion time;
automatic compare function; temperature sensor; internal
bandgap reference channel; operation in stop3; fully functional
from 3.6V to 1.8V
–
ACMP
— Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal bandgap reference voltage; outputs can
be optionally routed to TPM module; operation in stop3
–
SCI
— Full duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break
detection; wake up on active edge
–
SPI—
Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave mode;
MSB-first or LSB-first shifting
–
IIC
— IIC with up to 100 kbps with maximum bus loading;
Multi-master operation; Programmable slave address;
Interrupt driven byte-by-byte data transfer; supports broadcast
mode and 10-bit addressing
–
TPMx
— Two 2-channel (TPM1 and TPM2); Selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel;
–
TOD—
(Time Of Day) 8-bit quarter second counter with
match register; External clock source for precise time base,
time-of-day, calendar or task scheduling functions; Free
running on-chip low power oscillator (1 kHz) for cyclic
wake-up without external components.
• Input/Output
– 38 GPIOs, 2 output-only pins
– 8 KBI interrupts with selectable polarity
– Hysteresis and configurable pull up device on all input pins;
Configurable slew rate and drive strength on all output pins.
• Package Options
– 64-LQFP, 48-LQFP and 48-QFN
Table of Contents
1
2
3
Devices in the MC9S08LL16 Series . . . . . . . . . . . . . . 4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . 10
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 11
3.5 ESD Protection and Latch-Up Immunity . . . . . . 12
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Supply Current Characteristics . . . . . . . . . . . . . 25
3.8 External Oscillator (XOSCVLP) Characteristics 27
3.9 Internal Clock Source (ICS) Characteristics . . . 28
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .30
3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . .30
3.10.2TPM Module Timing . . . . . . . . . . . . . . . . .31
3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .32
3.11 Analog Comparator (ACMP) Electricals . . . . . . .35
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .35
3.13 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . .39
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .39
3.15 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .40
3.15.1Radiated Emissions . . . . . . . . . . . . . . . . .40
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.1 Device Numbering System . . . . . . . . . . . . . . . . .41
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
2
3
9/2008
10/2008
01/2009
Initial Release.
Updated electrical characteristics.
Corrected 48-Pin QFN/LQFP pinouts for pins 29, 30, 32, and 32 in
Figure 3.
Extracted Stop Mode Adders from the Supply Current table and created a Separate
table for the data (See
Table 10).
Added missing power consumption parameters in
Supply Current Characteristics (Table
9).
Completed all the TBDs.
Changed V
DDAD
to V
DDA
, V
SSAD
to V
SSA
, I
DDAD
to I
DDA.
Corrected the data in the
Table 8,
and added
|I
InT
|. Completed the Figure in the
4
07/21/2009
Section 3.6, “DC Characteristics.”
Corrected RI
DD
in FEI mode with all modules on, WI
DD
at 8 MHz, FEI mode with all
modules off, S2I
DD
, S3I
DD
; added ApS3I
DD
in the
Table 9.
Corrected E
TUE
, DNL, INL, E
ZS
, E
FS
, E
Q
, and E
IL
in the
Table 18.
5
6
7
10/13/2009
10/27/2010
1/23/2013
Updated R
PU
/R
PD
data in the
Table 8.
Added
Figure 5.
Changed the Max. of R
PU
/R
PD
at PTA[4:5], PTD[0:77] and PTE[0:7] to 69.5
kΩ
in the
Table 8.
Updated
|I
In
| in the
Table 8.
MC9S08LL16 Series MCU Data Sheet, Rev. 7
2
Freescale Semiconductor
ARM Technology
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