IDT72255LA10TFI datasheet, PDF

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IDT72255LA10TFI: Description16K X 18 OTHER FIFO, 8 ns, PQFP64; Categorystorage; File Size248KB，27 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT72255LA10TFI Overview

16K X 18 OTHER FIFO, 8 ns, PQFP64

IDT72255LA10TFI Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	8 ns
Processing package description	Plastic, TQFP-64
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, low PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
memory width	18
organize	16K × 18
storage density	294912 deg
operating mode	Synchronize
Number of digits	16384 words
Number of digits	16K
cycle	10 ns
Output enable	Yes
Memory IC type	Other first in first out

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CMOS SUPERSYNC FIFO™

8,192 x 18

16,384 x 18

Integrated Device Technology, Inc.

IDT72255LA

IDT72265LA

FEATURES:

• Choose among the following memory organizations:

IDT72255LA

8,192 x 18

IDT72265LA

16,384 x 18

• Pin-compatible with the IDT72275/72285 SuperSync FIFOs

• 10ns read/write cycle time (8ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and

writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the

64-pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72255LA/72265LA are exceptionally deep, high

speed, CMOS First-In-First-Out (FIFO) memories with clocked

read and write controls. These FIFOs offer numerous improve-

ments over previous SuperSync FIFOs, including the following:

• The limitation of the frequency of one clock input with

respect to the other has been removed. The Frequency

Select pin (FS) has been removed, thus it is no longer

necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed

and short.

FUNCTIONAL BLOCK DIAGRAM

WCLK

-D

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

8,192 x 18

16,384 x 18

FLAG

LOGIC

FWFT/SI

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

RESET

LOGIC

RCLK

-Q

SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

4670 drw 01

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE

APRIL 2001

DSC-4670/1

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