K4N26323AE-GC
128M GDDR2 SDRAM
128Mbit GDDR2 SDRAM
1M x 32Bit x 4 Banks
GDDR2 SDRAM
with Differential Data Strobe and DLL
Revision 1.7
January 2003
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Revision History
Revision 1.7 (January 23, 2003)
- Changed the device name from GDDR-II to GDDR2
128M GDDR2 SDRAM
Revision 1.6 (December 18, 2002)
- Typo corrected
Revision 1.5 (December 4, 2002)
- Typo corrected
Revision 1.4 (November 12, 2002)
- Changed the device name from DDR-II to GDDR-II
- Typo corrected
Revision 1.3 (November 8, 2002)
- Typo corrected
Revision 1.2 (November 5, 2002)
- Typo corrected
- Changed the Icc6 from 3mA to 7mA
Revision 1.1 (October 30, 2002)
- Typo corrected
Revision 1.0 (September 30, 2002)
- Changed tCK(max) from 4.5ns to 4.0ns
Revision 0.7 (September 12, 2002)
- Added IBIS curve in the spec
- Defined DC spec
- Typo corrected
- Defined Burst Write with AP (AL=0) Table.
- Defined On-die Termination Status of 2Banks System Table.
- Changed C
IN1
,C
IN2
,C
IN3
,C
out
and C
iN4
from 3.5pF to 3.0pF
- Removed CL(Cas Latency) 8 from the spec
- Changed VDD form 2.5V + 5% to 2.5V + 0.1V
- Changed speed bin from 500/400/333MHz to 500/450/400MHz
- Changed EMRS table
Revision 0.6 (February 28, 2002)
- Changed WL(write latency) from RL(read latency) -1 to AL(additive latency) +1
- Changed tIH/tSS during EMRS from 5ns to 0.5tCK
- Changed tRCDWR
- Changed package ball location of CK, /CK, CKE
- 2 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Revision 0.5 (January 2002)
- Eliminated DLLEN pin
- Power-up sequence
128M GDDR2 SDRAM
Revision 0.4 (January 2002)
- Changed EMRS Table
- Changed Self-Refresh exit mode
- Changed On-die Termination Control
- Changed OCD Control method
- Power-up sequence
Revision 0.3 (December 2001)
- Noted the ball names changed from DDR-1 and exchanged DQS and /DQS ball location.
- Added On-die termination control
- Changed OCD align mode entry / exit timing
- Added target value of
Data & DQS input/output capacitance(DQ
0
~DQ
31
)
- Added Table for auto precharge control
- Typo corrected.
Revision 0.2 (November 2001)
- Data Strobe Scheme is changed from DQS separation of Read DQS, Write DQS to Differential and Bi-directional DQS
- OCD adjustment
- Controlled DQ is changed from DQ0, WDQS2 to DQ23, DQS2 and /DQS2
Revision 0.1 (October 2001)
- Data Strobe Scheme is changed from Bi-directional DQS to DQS separation to Read DQS, Write DQS
- Package Ball layout is changed for mirror package.
- OCD adjustment
Controlled DQ is changed from DQ0, DQS0 to DQ23, WDQS2
- Added DM descriptions
- 1bank, 2bank system
- Added System Selection mode in EMRS table.
Revision 0.0 (August 2001)
- 3 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
1M x 32Bit x 4 Banks GDDR2 Synchronous DRAM
with Differential Data Strobe
FEATURES
• 2.5V + 0.1V power supply for device operation
• 1.8V + 0.1V power supply for I/O interface
• On-Die Termination for all inputs except CKE,ZQ
• Output Driver Strength adjustment by EMRS
• SSTL_18 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
- CAS latency : 5, 6, 7 (clock)
- Burst length : 4 only
- Burst type : sequential only
• Additive latency (AL): 0,1(clock)
• Read latency(RL) : CL+AL
• Write latency(WL) : AL+1
128M GDDR2 SDRAM
• Differential Data Strobes for Data-in, Date out ;
- 4 DQS and /DQS(one differential strobe per byte)
- Single Data Strobes by EMRS.
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
(16ms is under consideration)
• 144 Ball FBGA
• Maximum clock frequency up to 500MHz
• Maximum data rate up to 1Gbps/pin
• DLL for Address, CMD and outputs
ORDERING INFORMATION
Part NO.
K4N26323AE-GC20
K4N26323AE-GC22
K4N26323AE-GC25
Max Freq.
500MHz
450MHz
400MHz
Max Data Rate
1000Mbps/pin
900Mbps/pin
800Mbps/pin
SSTL_18
144 Ball FBGA
Interface
Package
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank GDDR2 SDRAM
The 4Mx32 GDDR2 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,976 words
by 32 bits, fabricated with SAMSUNG
’s
high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
- 4 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
PIN CONFIGURATION
Normal Package (Top View)
2
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ20
DQ21
DQ23
VREF
A0
128M GDDR2 SDRAM
3
/DQS0
DM0
DQ5
VDDQ
DQ16
DQ18
/DQS2
DM2
DQ22
A3
A2
A1
4
VSSQ
VDDQ
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
A10
A11
5
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
/RAS
BA0
6
DQ2
DQ1
VSSQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
RFU
2
NC
/CAS
7
DQ0
VDDQ
VDD
VSS
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
VDD
CKE
CK
8
DQ31
VDDQ
VDD
VSS
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
VDD
NC
/CK
9
DQ29
DQ30
VSSQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSS
RFU
1
ZQ
/WE
10
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
/CS
BA1
11
VSSQ
VDDQ
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
A9
A8/AP
12
/DQS3
DM3
DQ26
VDDQ
DQ15
DQ13
/DQS1
DM1
DQ9
A4
A5
A6
13
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ11
DQ10
DQ8
VREF
A7
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. (M,13) VREF for CMD and ADDRESS
4. (M,2) VREF for Data input
- 5 -
Rev. 1.7 (Jan. 2003)
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