K7I161882B-FC30 datasheet, PDF

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K7I161882B-FC30: Description512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM; Categorystorage storage; File Size365KB，17 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7I161882B-FC30 Overview

512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

K7I161882B-FC30 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	303 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	18874368 bi
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.2 A
Minimum standby current	1.7 V
Maximum slew rate	0.5 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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K7I163682B

K7I161882B

Document Title

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM

Revision History

Rev. No.

0.0

0.1

History

1. Initial document.

1. Add the speed bin (-33, -30)

2. Delete the speed bin (-25, -13)

1. Change the Boundary scan exit order.

2. Correct the Overshoot and Undershoot timing diagram.

1. Add the speed bin (-25)

1. Correct the JTAG ID register definition

2. Correct the AC timing parameter (delete the tKHKH Max value)

1. Change the Maximum Clock cycle time.

2. Correct the 165FBGA package ball size.

1. Add the power up/down sequencing comment.

2. Update the DC current parameter (Icc and Isb).

3. Change the Max. speed bin from -33 to -30.

1. Change the ISB1.

Speed Bin

-30

-25

-20

-16

1.0

2.0

1. Final spec release

1. Delete the x8 Org.

2. Delete the 300MHz speed bin

1. Add the 300MHz speed bin

1. Change the stand-by current(I

SB1

)

before

after

Isb1

-30 :

230

260

-25 :

210

240

-20 :

190

220

-16 :

170

200

From

200

180

160

140

230

210

190

170

Oct. 31, 2003

Nov. 28, 2003

Final

Draft Date

Oct. 23. 2002

Oct. 24. 2002

Remark

Advance

Premilinary

0.2

Dec. 16, 2002

Premilinary

0.3

0.4

Jan. 27, 2003

Mar. 20, 2003

Premilinary

0.5

April. 4, 2003

Premilinary

0.6

June. 20, 2003

Premilinary

0.7

Oct. 20. 2003

Premilinary

3.0

3.1

June. 18, 2004

July. 28, 2004

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

July. 2004

Rev 3.1

K7I163682B

K7I161882B

GENERAL DESCRIPTION

512Kx36 & 1Mx18 DDRII CIO b2 SRAM

The K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O

Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read data are referenced to echo clock ( CQ or CQ ) outputs.

Read address and write address are registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using LD for port selection.

Byte write operation is supported with BW

and BW

( BW

and BW

pins for x18 ( x36 ) device.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7I163682B and K7I161882B are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K insted of C and C.

When the LD is disabled after a read operation, the K7I163682B and K7I161882B will first complete

burst read operation before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Echo clock operation

To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,

which are synchronized with internal data output.

Echo clocks run free during normal operation.

The Echo clock is triggered by internal output clock signal, and transfered to external through same structures

as output driver.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

-5-

July. 2004

Rev 3.1

K7I161882B-FC30 Related Products

	K7I161882B-FC30	K7I163682B	K7I161882B-FC16	K7I161882B-FC25	GS8JQ	K7I163682B-FC16	K7I163682B-FC25	K7I163682B-FC20	K7I163682B-FC30
Description	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	Surface Mount General Purpose Rectifier	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM	512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
Is it Rohs certified?	incompatible	-	incompatible	incompatible	-	incompatible	incompatible	incompatible	incompatible
Maker	SAMSUNG	-	SAMSUNG	SAMSUNG	-	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	-	BGA	-	-	BGA	-	BGA	BGA
package instruction	LBGA, BGA165,11X15,40	-	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	-	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40
Contacts	165	-	165	-	-	165	-	165	165
Reach Compliance Code	unknow	-	compli	unknow	-	unknow	unknow	unknow	unknow
ECCN code	3A991.B.2.A	-	3A991.B.2.A	-	-	3A991.B.2.A	-	3A991.B.2.A	3A991.B.2.A
Maximum access time	0.45 ns	-	0.5 ns	-	-	0.5 ns	0.45 ns	0.45 ns	0.45 ns
Other features	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	-	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	303 MHz	-	167 MHz	-	-	167 MHz	250 MHz	200 MHz	303 MHz
I/O type	COMMON	-	COMMON	-	-	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B165	-	R-PBGA-B165	-	-	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e0	-	e0	-	-	e0	e0	e0	e0
length	17 mm	-	17 mm	-	-	17 mm	15 mm	17 mm	17 mm
memory density	18874368 bi	-	18874368 bi	-	-	18874368 bi	18874368 bi	18874368 bi	18874368 bi
Memory IC Type	DDR SRAM	-	DDR SRAM	-	-	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	18	-	18	-	-	36	36	36	36
Number of functions	1	-	1	-	-	1	1	1	1
Number of terminals	165	-	165	-	-	165	165	165	165
word count	1048576 words	-	1048576 words	-	-	524288 words	524288 words	524288 words	524288 words
character code	1000000	-	1000000	-	-	512000	512000	512000	512000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	-	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	-	70 °C	-	-	70 °C	70 °C	70 °C	70 °C
organize	1MX18	-	1MX18	-	-	512KX36	512KX36	512KX36	512KX36
Output characteristics	3-STATE	-	3-STATE	-	-	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	-	LBGA	-	-	LBGA	LBGA	LBGA	LBGA
Encapsulate equivalent code	BGA165,11X15,40	-	BGA165,11X15,40	-	-	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40
Package shape	RECTANGULAR	-	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	-	GRID ARRAY, LOW PROFILE	-	-	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	-	PARALLEL	-	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	-	-	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED
power supply	1.5/1.8,1.8 V	-	1.5/1.8,1.8 V	-	-	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V
Certification status	Not Qualified	-	Not Qualified	-	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	-	1.4 mm	-	-	1.4 mm	1.4 mm	1.4 mm	1.4 mm
Maximum standby current	0.2 A	-	0.14 A	-	-	0.14 A	0.18 A	0.16 A	0.2 A
Minimum standby current	1.7 V	-	1.7 V	-	-	1.7 V	1.7 V	1.7 V	1.7 V
Maximum slew rate	0.5 mA	-	0.35 mA	-	-	0.45 mA	0.55 mA	0.5 mA	0.6 mA
Maximum supply voltage (Vsup)	1.9 V	-	1.9 V	-	-	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	-	1.7 V	-	-	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	-	1.8 V	-	-	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	-	YES	-	-	YES	YES	YES	YES
technology	CMOS	-	CMOS	-	-	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	-	BALL	-	-	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	-	1 mm	-	-	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	-	BOTTOM	-	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	-	-	NOT SPECIFIED	40	NOT SPECIFIED	NOT SPECIFIED
width	15 mm	-	15 mm	-	-	15 mm	13 mm	15 mm	15 mm

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