Philips Semiconductors
Product specification
Octal registered transceivers
74F543
74F544
FEATURES
74F543, 74F544
Octal registered transceiver, non-inverting (3-State)
Octal registered transceiver, inverting 93-State)
FUNCTIONAL DESCRIPTION
The 74F543 and 74F544 contain two sets of eight D-type latches,
with separate input and controls for each set. For data flow from A to
B, for example, the A-to-B Enable (EAB) input must be Low in order
to enter data from A0 - A7 or take data from B0 - B7, as indicated in
the Function Table. With EAB Low, a Low signal on the A-to-B Latch
Enable (LEAB) input makes the A-to-B latches transparent; a
subsequent Low-to-High transition for the LEAB signal puts the
A latches in the storage mode and their outputs no longer change
with the A inputs. With EAB and OEAB both Low, the 3-State
B output buffers are active and display the data present at the
outputs of the A latches. Control of data flow from B to A is similar,
but using the EBA, LEBA, and OEBA inputs.
TYPICAL
PROPAGATION
DELAY
6.0ns
6.5ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
80mA
95mA
•
Combines74F245 and 74F373 type functions in one chip
•
8-bit octal transceiver with D-type latch
•
74F543 Non-inverting
•
Back-to-back registers for storage
•
Separate controls for data flow in each direction
•
A outputs sink 20mA and source 3mA
•
B outputs sink 64mA and source 15mA
•
3-State outputs for bus-oriented applications
•
74F543 available in SSOP Type II package
DESCRIPTION
The 74F543 and 74F544 Octal Registered Transceivers contain two
sets of D-type latches for temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB, LEBA) and Output Enable
(OEAB, OEBA) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
data flow. While the 74F543 has non-inverting data path, the 74F544
inverts data in both directions. The A outputs are guaranteed to sink
24mA, while the B outputs are rated for 64mA.
74F544 Inverting
TYPE
74F543
74F544
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
A
= 0°C to +70°C
N74F543N,
N74F544N
N74F543D,
N74F544D
74F543DB
DRAWING
NUMBER
SOT222–1
SOT137-1
SOT340-1
24-pin plastic skinny DIP (300mil)
24-pin plastic SOL
24-pin plastic SSOP Type II
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0 - A7
B0 - B7
OEAB
74F543
74F544
OEBA
EAB
EBA
LEAB
LEBA
74F543
A0 - A7
B0 - B7
74F544
A0 - A7
B0 - B7
DESCRIPTION
Port A, 3-State inputs
Port B, 3-State inputs
A-to-B Output Enable input (Active Low)
B-to-A Output Enable input (Active Low)
A-to-B Enable input (Active Low)
B-to-A Enable input (Active Low)
A-to-B Latch Enable input (Active Low)
B-to-A Latch Enable input (Active Low)
Port A, 3-State outputs
Port B, 3-State outputs
Port A, 3-State outputs
Port B, 3-State outputs
74F(U.L.)
HIGH/LOW
3.5/1.0
3.5/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
1.0/1.0
1.0/1.0
150/40
750/106.7
150/40
750/106.7
LOAD VALUE
HIGH/LOW
70µA/0.6mA
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
15mA/64mA
3.0mA/24mA
15mA/64mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High State and 0.6mA in the Low state.
1994 Dec 5
2
853-0874 14379
Philips Semiconductors
Product specification
Octal registered transceivers
74F543, 74F544
PIN CONFIGURATION – 74F544
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
7
8
9
24 V
CC
23 EBA
22 B0
LOGIC SYMBOL – 74F544
3
4
5
6
7
8
9
10
A0 A1 A2 A3 A4 A5 A6 A7
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
V
CC
= Pin 24
GND = Pin 12
22 21 20 19 18 17 16 15
B0 B1 B2 B3 B4 B5 B6 B7
11
23
14
1
EAB
EBA
LEAB
LEBA
OEAB
OEBA
13
2
A7 10
EAB 11
GND 12
SF00240
SF00242
LOGIC SYMBOL (IEEE/IEC) – 74F544
2
23
1
13
11
14
IEN3
G1
1C5
2EN4
G2
2C6
FUNCTION TABLE for 74F543 and 74F544
INPUTS
OEXX
H
X
L
L
22
21
20
19
18
17
16
15
OUTPUTS
DATA
X
X
h
l
h
l
H
L
X
74F543
Z
Z
Z
Z
H
L
H
L
NC
74F544
Z
Z
Z
Z
L
H
L
H
NC
STATUS
Disabled
Disabled
Disable +
Latch
Latch +
Display
Transparent
Hold
EXX
X
H
↑
↑
L
L
L
L
L
LEXX
X
X
L
L
↑
↑
L
L
H
3
4
5
6
7
8
9
10
3
6D
5D
4
L
L
L
L
L
H
L
h
SF00241
= High voltage level
= Low voltage level
= High state must be present one setup time before the
Low-to-High transition of LEXX or EXX (XX=AB or BA)
l
= Low state must be present one setup time before the
Low-to-High transition of LEXX or EXX (XX=AB or BA)
↑
= Low-to-High transition of LEXX or EXX XX = AB or BA
X = Don’t care
NC = No change
Z = High impedance “off” state
1994 Dec 5
4
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