IDT72V3684 datasheet, PDF - EEWORLD Datasheet

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IDT72V3684: Description3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING; File Size341KB，36 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT72V3684 Overview

3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING

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3.3 VOLT CMOS SyncBiFIFO

WITH BUS-MATCHING

16,384 x 36 x 2

IDT72V3684

32,768 x 36 x 2

IDT72V3694

65,536 x 36 x 2

IDT72V36104

FEATURES

•

Memory storage capacity:

IDT72V3684 – 16,384 x 36 x 2

IDT72V3694 – 32,768 x 36 x 2

IDT72V36104 – 65,536 x 36 x 2

Clock frequencies up to 100 MHz (6.5ns access time)

Two independent clocked FIFOs buffering data in opposite

directions

Select IDT Standard timing (using

EFA, EFB, FFA,

and

FFB

flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

Programmable Almost-Empty and Almost-Full flags; each has five

default offsets (8, 16, 64, 256 and 1,024 )

Serial or parallel programming of partial flags

Retransmit Capability

•

Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

Big- or Little-Endian format for word and byte bus sizes

Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

Mailbox bypass registers for each FIFO

Free-running CLKA and CLKB may be asynchronous or coincident

(simultaneous reading and writing of data on a single clock edge

is permitted)

Auto power down minimizes power dissipation

Available in space saving 128-pin Thin Quad Flatpack (TQFP)

Pin compatible to the lower density parts, IDT72V3624/72V3634/

72V3644/72V3654/72V3664/72V3674

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

Output Bus-

Matching

Input

Output

CLKA

CSA

W/RA

ENA

MBA

MRS1

PRS1

Port-A

Control

Logic

RAM ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

FIFO1,

Mail1

Reset

Logic

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FS2

FS0/SD

FS1/SEN

-A

EFA/ORA

AEA

FIFO1

Programmable Flag

Offset Registers

FIFO2

Timing

Mode

FWFT

-B

Status Flag

Logic

Read

Pointer

Write

Pointer

FFB/IRB

AFB

RT1

RTM

RT2

Output

Input Bus-

Matching

16,384 x 36

32,768 x 36

65,536 x 36

Mail 2

Input

FIFO1 and

FIFO2

Retransmit

Logic

RAM ARRAY

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

Port-B

Control

Logic

4677 drw01

MBF2

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

CLKB

CSB

W/RB

ENB

MBB

SIZE

COMMERCIAL TEMPERATURE RANGE

2009

FEBRUARY 2009

DSC-4677/8

IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO

WITH

BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol

FS0/SD

Name

I/O

Description

Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master

Serial Data

Reset, FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three offset

1,024), parallel load from Port A, and serial load.

FS1/SEN Flag Offset Select 1/ I

Serial Enable,

When serial load is selected for flag offset register programming, FS1/SEN is used as an enable

synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load

(1)

FS2

Flag Offset Select 2

I the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset

registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write

stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB.

MBA

Port A Mailbox

I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35

Select

outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level

selects FIFO2 output register data for output.

MBB

Port B Mailbox

Select

Mail1 Register

Flag

Mail2 Register

Flag

FIFO1 Master

Reset

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35

outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level

selects FIFO1 output register data for output.

MBF1

is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1

MBF1

is LOW.

MBF1

is set HIGH by a LOW-to-HIGH transition of CLKB when a

Port B read is selected and MBB is HIGH.

MBF1

is set HIGH following either a Master or Partial Reset of FIFO1.

MBF2

is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2

MBF2

is LOW.

MBF2

is set HIGH by a LOW-to-HIGH transition of CLKA when a Port

A read is selected and MBA is HIGH.

MBF2

is set HIGH following either a Master or Partial Reset of FIFO2.

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port

B output register to all zeroes. A LOW-to-HIGH transition on

MRS1

selects the programming method (serial or parallel)

and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and

endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must

occur while

MRS1

is LOW.

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A

output register to all zeroes. A LOW-to-HIGH transition on

MRS2,

toggled simultaneously with

MRS1,

selects the

programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to-

HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while

MRS2

is LOW.

This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.

If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read

and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset,

the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable

flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read

pointer only to the first memory location.

This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.

If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read

and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag

settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer

only to the first memory location.

This pin is used in conjunction with the

RT1

and

RT2

pins. When RTM is HIGH a Retransmit is performed on

FIFO1 or FIFO2 respectively.

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH

selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port

B. The level of SIZE must be static throughout device operation

A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH

transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH

transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when

W/RB

is LOW.

MBF1

MBF2

MRS1

MRS2

FIFO2 Master

Reset

PRS1/

RT1

Partial Reset/

Retransmit FIFO1

PRS2/

RT2

Partial Reset/

Retransmit FIFO2

RTM

SIZE

(1)

Retransmit Mode

Bus Size Select

W/RA

W/RB

Port-A Write/

Read Select

Port-B Write/

Read Select

NOTE:

1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V

IDT72V3684 Related Products

	IDT72V3684	IDT72V36104	IDT72V36104L10PF	IDT72V36104L15PF	IDT72V3684L10PF	IDT72V3694	IDT72V3684L15PF	IDT72V3694L15PF	IDT72V3694L10PF
Description	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING	3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING

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