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MC10H159FNR2

Description
Encoders, Decoders, Multiplexers u0026 Demultiplexers Quad 2-Input Mux
Categorylogic    logic   
File Size148KB,7 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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MC10H159FNR2 Overview

Encoders, Decoders, Multiplexers u0026 Demultiplexers Quad 2-Input Mux

MC10H159FNR2 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeQLCC
package instructionPLASTIC, LCC-20
Contacts20
Reach Compliance Codenot_compliant
Factory Lead Time1 week
series10H
JESD-30 codeS-PQCC-J20
JESD-609 codee0
length8.965 mm
Logic integrated circuit typeMULTIPLEXER
Number of functions4
Number of entries2
Output times1
Number of terminals20
Maximum operating temperature75 °C
Minimum operating temperature
Output characteristicsOPEN-EMITTER
Output polarityINVERTED
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC20,.4SQ
Package shapeSQUARE
Package formCHIP CARRIER
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)240
Maximum supply current (ICC)58 mA
Prop。Delay @ Nom-Sup3.2 ns
propagation delay (tpd)2.2 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn80Pb20)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width8.965 mm
MC10H159
Quad 2−Input Multiplexer
(Inverting)
Description
The MC10H159 is a quad 2−input multiplexer with enable. This
MECL 10H™ part is a functional/pinout duplication of the standard
MECL 10K™ family part, with 100% improvement in propagation
delay and no increase in power−supply current.
Features
http://onsemi.com
MARKING DIAGRAMS*
16
MC10H159L
AWLYYWW
CDIP−16
L SUFFIX
CASE 620A
1
Propagation Delay, 1.5 ns Typical
Power Dissipation, 218 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K Compatible
Pb−Free Packages are Available*
TRUTH TABLE
Enable
L
L
L
L
H
Select
L
L
H
H
X
D0
X
X
L
H
X
D1
L
H
X
X
X
Q
H
L
H
L
L
16
16
1
PDIP−16
P SUFFIX
CASE 648
1
MC10H159P
AWLYYWWG
10H159
ALYWG
DIP
PIN ASSIGNMENT
Q0
Q1
D11
D10
D01
D00
ENABLE
V
EE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q2
Q3
D20
D21
D30
D31
SELECT
SOEIAJ−16
CASE 966
1 20
20 1
PLLC−20
FN SUFFIX
CASE 775
A
WL, L
YY, Y
WW, W
G
10H159G
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
*For additional marking information, refer to
Application Note AND8002/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
February, 2006
Rev. 7
1
Publication Order Number:
MC10H159/D
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