FPGA calls Ming Deyang

Mingdeyang FPGA dialing video tutorial

• Chapter 1：Course Introduction (10 minutes and 24 seconds)

• Chapter 2：Questasim software installation (16 minutes and 42 seconds)

• Chapter 3：QuartusII software installation (15 minutes and 47 seconds)

• Chapter 4：GVIM installation and use (13 minutes and 22 seconds)

• Chapter 5：The first board routine (8 minutes and 27 seconds)

• Chapter 6：Quartus usage exercise 1 instructions (2 minutes and 39 seconds)

• Chapter 7：QuartusⅡUsing Exercise 1 Answers (3 minutes and 10 seconds)

• Chapter 8：Detailed explanation of verilog code (7 minutes and 33 seconds)

• Chapter 9：Introductory Exercise 1 Instructions (2 minutes and 49 seconds)

• Chapter 10：Answers to introductory exercise 1 (3 minutes and 59 seconds)

• Chapter 11：Introductory Exercise 2 Instructions (2 minutes and 56 seconds)

• Chapter 12：Answers to introductory exercise 2 (3 minutes and 8 seconds)

• Chapter 13：Introductory Exercise 3 Instructions (3 minutes and 21 seconds)

• Chapter 14：Answers to introductory exercise 3 (4 minutes and 49 seconds)

• Chapter 15：Introductory Exercise 4 Instructions (3 minutes and 0 seconds)

• Chapter 16：Answers to introductory exercise 4 (5 minutes and 32 seconds)

• Chapter 17：modelsim usage (13 minutes and 34 seconds)

• Chapter 18：How to view modelsim waveforms (17 minutes and 3 seconds)

• Chapter 19：Modelsim Elementary Exercise 1 Description (3 minutes and 16 seconds)

• Chapter 20：Modelsim Elementary Exercise 1 Answers (15 minutes and 41 seconds)

• Chapter 21：Modelsim Elementary Exercise 2 Description (3 minutes and 6 seconds)

• Chapter 22：Modelsim Elementary Exercise 2 Answers (8 minutes and 3 seconds)

• Chapter 23：Modelsim Elementary Exercise 3 Description (3 minutes and 19 seconds)

• Chapter 24：Modelsim Elementary Exercise 3 Answers (4 minutes and 58 seconds)

• Chapter 25：Modelsim Level 1 Exercise 1 Description (2 minutes and 57 seconds)

• Chapter 26：Modelsim Level 1 Exercise 1 Answers (3 minutes and 52 seconds)

• Chapter 27：Modelsim Level 1 Exercise 2 Description (4 minutes and 25 seconds)

• Chapter 28：Modelsim Level 1 Exercise 2 Answers (3 minutes and 41 seconds)

• Chapter 29：Quickly master verilog-programming (23 minutes and 18 seconds)

• Chapter 30：Verilog quick mastery of module instantiation (8 minutes and 26 seconds)

• Chapter 31：Operators to quickly master verilog (15 minutes and 23 seconds)

• Chapter 32：Module design instructions for quick mastering of verilog (3 minutes and 29 seconds)

• Chapter 33：Verilog quick mastery of module design answers (12 minutes and 24 seconds)

• Chapter 34：Instructions for complex module design to quickly master verilog (3 minutes and 23 seconds)

• Chapter 35：Verilog quick mastery of complex module design answers (17 minutes and 52 seconds)

• Chapter 36：Verilog Quick Master Exercise 1 Instructions (2 minutes and 53 seconds)

• Chapter 37：Verilog Quick Master Exercise 2 Instructions (2 minutes and 53 seconds)

• Chapter 38：Verilog Quick Master Exercise 3 Instructions (2 minutes and 53 seconds)

• Chapter 39：Verilog Quick Master Exercise 4 Instructions (3 minutes and 25 seconds)

• Chapter 40：Verilog Quick Master Exercise 5 Instructions (3 minutes and 22 seconds)

• Chapter 41：Module design template (9 minutes and 53 seconds)

• Chapter 42：Test file writing skills (12 minutes and 45 seconds)

• Chapter 43：Test file template (7 minutes and 26 seconds)

• Chapter 44：Test file writing exercise 1 instructions (2 minutes and 49 seconds)

• Chapter 45：Test file writing exercise 1 answers (13 minutes and 54 seconds)

• Chapter 46：The concept of packaging (16 minutes and 5 seconds)

• Chapter 47：Test file writing exercise 2 instructions (12 minutes and 4 seconds)

• Chapter 48：Test file writing exercise 2 answers (21 minutes and 3 seconds)

• Chapter 49：Test file writing exercise 3 instructions (3 minutes and 37 seconds)

• Chapter 50：Test file writing exercise 3 answers (13 minutes and 31 seconds)

• Chapter 51：Test file writing exercise 4 instructions (3 minutes and 32 seconds)

• Chapter 52：Test file writing exercise 4 answers (7 minutes and 7 seconds)

• Chapter 53：Test file writing exercise 5 instructions (2 minutes and 56 seconds)

• Chapter 54：Test file writing exercise 5 answers (15 minutes and 9 seconds)

• Chapter 55：Mingdeyang norms (43 minutes and 20 seconds)

• Chapter 56：Always design only one signal (19 minutes and 24 seconds)

• Chapter 57：Clock reset design specifications (8 minutes and 53 seconds)

• Chapter 58：Combinational logic completion condition (5 minutes and 45 seconds)

• Chapter 59：always Exercise 1 Instructions (8 minutes and 49 seconds)

• Chapter 60：always exercise 1 answers (29 minutes and 30 seconds)

• Chapter 61：Mingdeyang template summary (9 minutes and 27 seconds)

• Chapter 62：Use of GVIM 2 (26 minutes and 28 seconds)

• Chapter 63：signaltapII use (18 minutes and 53 seconds)

• Chapter 64：Waveform comparison method (7 minutes and 20 seconds)

• Chapter 65：Use of counters (27 minutes and 31 seconds)

• Chapter 66：Counter Exercise 1 Instructions (6 minutes and 2 seconds)

• Chapter 67：Counter Exercise 1 Answers (13 minutes and 14 seconds)

• Chapter 68：Counter Exercise 2 Instructions (3 minutes and 47 seconds)

• Chapter 69：Counter Exercise 2 Answers (18 minutes and 45 seconds)

• Chapter 70：Counter Exercise 3 Instructions (2 minutes and 41 seconds)

• Chapter 71：Counter Exercise 3 Answers (12 minutes and 37 seconds)

• Chapter 72：Counter Exercise 4 Instructions (5 minutes and 26 seconds)

• Chapter 73：Counter Exercise 4 Answers (12 minutes and 6 seconds)

• Chapter 74：Counter Exercise 5 Instructions (2 minutes and 34 seconds)

• Chapter 75：Counter Exercise 5 Answers (13 minutes and 14 seconds)

• Chapter 76：Counter Exercise 6 Instructions (3 minutes and 18 seconds)

• Chapter 77：Counter Exercise 6 Answers (15 minutes and 49 seconds)

• Chapter 78：Counter Exercise 7 Instructions (10 minutes and 19 seconds)

• Chapter 79：Counter Exercise 7 Answers (38 minutes and 12 seconds)

• Chapter 80：State machine design principles (15 minutes and 25 seconds)

• Chapter 81：State Machine Exercise 1 Instructions (2 minutes and 41 seconds)

• Chapter 82：State machine exercise 1 answers (5 minutes and 35 seconds)

• Chapter 83：Waveform comparison method (7 minutes and 43 seconds)

• Chapter 84：State Machine Exercise 2 Instructions (2 minutes and 3 seconds)

• Chapter 85：State Machine Exercise 2 Answers (9 minutes and 38 seconds)

• Chapter 86：State Machine Exercise 3 Instructions (3 minutes and 7 seconds)

• Chapter 87：State machine exercise 3 answers (8 minutes and 57 seconds)

• Chapter 88：State Machine Exercise 4 Instructions (1 minutes and 44 seconds)

• Chapter 89：State Machine Exercise 4 Answers (10 minutes and 12 seconds)

• Chapter 90：State Machine Exercise 5 Instructions (7 minutes and 30 seconds)

• Chapter 91：State machine exercise 5 answers (33 minutes and 11 seconds)

• Chapter 92：FPGA timing principles (23 minutes and 34 seconds)

• Chapter 93：Analyze timing with quartus (19 minutes and 8 seconds)

• Chapter 94：FPGA Timing Exercise 1 Instructions (1 minutes and 19 seconds)

• Chapter 95：Why pipeline (9 minutes and 6 seconds)

• Chapter 96：Assembly Line Exercise 1 Instructions (3 minutes and 20 seconds)

• Chapter 97：Assembly line exercise 1 answers (2 minutes and 10 seconds)

• Chapter 98：Assembly Line Exercise 2 Instructions (1 minutes and 34 seconds)

• Chapter 99：Assembly line exercise 2 answers (5 minutes and 13 seconds)

• Chapter 100：Assembly Line Exercise 3 Instructions (1 minutes and 53 seconds)

• Chapter 101：Assembly line exercise 3 answers (4 minutes and 54 seconds)

• Chapter 102：Assembly Line Exercise 4 Instructions (2 minutes and 43 seconds)

• Chapter 103：Assembly line exercise 4 answers (18 minutes and 1 seconds)

• Chapter 104：Assembly Line Exercise 5 Instructions (3 minutes and 44 seconds)

• Chapter 105：Assembly line exercise 5 answers (26 minutes and 34 seconds)

• Chapter 106：The importance of simple code (4 minutes and 49 seconds)

• Chapter 107：Code Simplification Exercise 1 Instructions (1 minutes and 56 seconds)

• Chapter 108：Code Simplification Exercise 1 Answers (13 minutes and 28 seconds)

• Chapter 109：Code Simplification Exercise 2 Instructions (1 minutes and 16 seconds)

• Chapter 110：Code Simplification Exercise 2 Answers (14 minutes and 28 seconds)

• Chapter 111：Code Simplification Exercise 3 Instructions (1 minutes and 23 seconds)

• Chapter 112：Code Simplification Exercise 3 Answers (14 minutes and 11 seconds)

• Chapter 113：FIFO principle (19 minutes and 49 seconds)

• Chapter 114：IP core that generates FIFO (11 minutes and 18 seconds)

• Chapter 115：How to verify code with IP cores (4 minutes and 59 seconds)

• Chapter 116：FIFO Exercise 1 Instructions (5 minutes and 46 seconds)

• Chapter 117：FIFO Exercise 1 Answers (10 minutes and 21 seconds)

• Chapter 118：FIFO Exercise 2 Instructions (4 minutes and 8 seconds)

• Chapter 119：FIFO Exercise 2 Answers (8 minutes and 8 seconds)

• Chapter 120：FIFO Exercise 3 Instructions (5 minutes and 20 seconds)

• Chapter 121：FIFO exercise 3 answers (8 minutes and 39 seconds)

• Chapter 122：What is asynchronous timing (24 minutes and 0 seconds)

• Chapter 123：tri-state gate (7 minutes and 36 seconds)

• Chapter 124：Asynchronous Timing Exercise 1 Instructions (2 minutes and 55 seconds)

• Chapter 125：Asynchronous timing exercise 1 answers (8 minutes and 36 seconds)

• Chapter 126：Asynchronous Timing Exercise 2 Instructions (18 minutes and 49 seconds)

• Chapter 127：Asynchronous timing exercise 2 interface timing parameters (21 minutes and 6 seconds)

• Chapter 128：Asynchronous timing exercise 2 test file (5 minutes and 29 seconds)

• Chapter 129：Asynchronous timing exercise 2 answers (19 minutes and 54 seconds)

• Chapter 130：Use GVIM to create templates (6 minutes and 59 seconds)