• Duration:9 minutes and 13 seconds
  • Date:2018/05/04
  • Uploader:量子阱
Introduction
keywords:
The tutorial adopts a step-by-step approach to explain. Through the study of this tutorial, you can have a comprehensive and in-depth grasp of the basic principles of embedded real-time operating systems, and be able to understand μC/OS including the kernel, task management, time and interrupt management, semaphore management, and mutually exclusive semaphores. The source code of management, event flag group management, message mailbox management, message queue management, and memory management can transplant μC/OS to different platforms, and you can know what is happening and why during the transplanting process, and you will not know how to do it. Difficulties and errors that occur when forced transplantation without mastering μC/OS.
Unfold ↓

You Might Like

Recommended Posts

's evaluation of Yidian Power
First of all, let me show you my achievements: loveliness:Now let me talk about my evaluation of Easy Power Supply: First of all, the chip is small in size and highly integrated. However, it mostly us
m357482894 Analogue and Mixed Signal
I'm depressed today
I found it troublesome to debug the C1 version of 9B96 on the board, so I replaced it with a C3 version with a hot hair dryer. It turned out to be easy to blow it off, but there was a lack of cold sol
fengzhang2002 Microcontroller MCU
Program for single chip password lock
I have a program for a single-chip password lock. The specific function is [color=magenta] This example shows how to use 8051, LCD display and 4ⅹ4 keypad to make a password lock. PORT 1 is connected t
LINGERZHE MCU
A puzzled question in CCS
Hey guys, I'm a newbie and I have a question I don't understand.After creating a new project and adding *.lib and *.c files, the program can run normally. Why do I need to add *.asm and *.cmd? And if
paddydong Analogue and Mixed Signal
About SPI mode setting
For SPI communication, there are only four pins: MOSI, MISO, CS, and CLK. SPI has four modes. So how do you set the various modes when using SPI? There are no clock polarity and phase pins?
shijizai 51mcu
[FPGA Design Tips] Several concepts about FPGA clocks: delay, intermediate state and speed
InWhen the delay of data transfer between registers exceeds one clock cycle, the downstream register cannot sample the upstream data given in the current clock cycle in the next clock cycle, and an er
eeleader FPGA/CPLD

Recommended Content

Hot ArticlesMore

可能感兴趣器件

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号