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Location:Training / Embedded Development / RISC-V 5th workshop / SCRx a family of state of the art RISC V synthesizable cores Alexander Redkin, Synta

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SCRx a family of state of the art RISC V synthesizable cores Alexander Redkin, Synta
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Chapter 1：5th RISC V Workshop Introduction Rick O’Connor, RISC V; Dom Rizzo, Google
Chapter 2：RISC V @ UC San Diego Michael B Taylor, UC San Diego
Chapter 3：Updates on PULPino Florian Zaruba, ETH Zurich 1
Chapter 4：SiFive FE300 and low cost HiFive Development Board Jack Kang, SiFive
Chapter 5：Rapid silicon prototyping and production for RISC V SoCs Neil Hand, Codasip 1
Chapter 6：VM threads an alternative model for virtual machines on RISC V Ron Minnich, Google
Chapter 7：A memory model for RISC V Muralidaran Vijayaraghavan, MIT
Chapter 8：A Memory Consistency Model for RISC V Caroline Trippel, Princeton University
Chapter 9：Keynote Address Trust, Transparency and Simplicity Eric Grosse, Google
Chapter 10：RISC V Foundation Update Rick O’Connor, RISC V Foundation
Chapter 11：RISC V Marketing Committee Update Arun Thomas, BAE Systems
Chapter 12：RISC V Technical Committee Update Yunsup Lee, SiFive
Chapter 13：Rocket Chip Project a nonprofit foundation for hosting open source RISC V implementations
Chapter 14：128 bit addressing in RISC V and security Steve Wallach, Micron
Chapter 15：The Challenges of Securing and Authenticating Embedded Devices and a Suggested Approach
Chapter 16：Sanctum Minimal Hardware Extensions for Strong Software Isolation Ilia Lebedev, MIT
Chapter 17：Joined up debugging and analysis in the RISC V world Gajinder Panesar, UltraSoC
Chapter 18：Poster Demo Previews ~ 2min per presenter
Chapter 19：RISC V Workshop Introduction Rick O’Connor, RISC V; Dom Rizzo, Google
Chapter 20：“V” Vector Extension Proposal Krste Asanovic, UC Berkeley & SiFive
Chapter 21：Towards Thousand Core RISC V Shared Memory Systems Quan Nguyen,MIT
Chapter 22：SCRx a family of state of the art RISC V synthesizable cores Alexander Redkin, Synta
Chapter 23：Enabling hardware software co design with RISC V and LLVM Alex Bradbury, lowRISC
Chapter 24：VM threads an alternative model for virtual machines on RISC V Ron Minnich, Google
Chapter 25：Enabling low power, smartphone like graphical UIs for RISC V SoCs Michael Gielda, Ant
Chapter 26：A Fast Instruction Set Simulator for RISC V Maxim Maslov, Esperanto
Chapter 27：Go on RISC VBenjamin Barenblat, Michael Pratt, Google
Chapter 28：A Java Virtual Machine for RISC V Porting the Jikes RVM Martin Maas, UC Berkeley
Chapter 29：YoPuzzle A mRISC V development platform for next generations Elkim Roa, Universidad
Chapter 30：RISC V Community needs Peripheral Cores Elkim Roa, Universidad Industrial de Santander
Chapter 31：Sub microsecond Adaptive Voltage Scaling in a 28nm RISC V SoC Ben Keller, UC Berkeley
Chapter 32：Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC V Processor Brian Zimmer
Chapter 33：RISC V Workshop Conclusion Rick O’Connor, RISC V Foundation; Dom Rizzo, Google

Duration：8 minutes and 4 seconds
Date：2021/03/27

Uploader：Lemontree

Introduction

keywords： risc v

RISC-V 5th workshop

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