Verilog language BUG help, thank you! [p=24, null, left][color=rgb(102, 102, 102)]Now I encounter a problem. For the following code always(@posedge clk) begin if(a==1'b1 && cnt<5'd18)[/color][/p][p=24
The first China-Europe VR Game Developer Competition, the world's highest-level VR game developer competition in 2016, has kicked off. Co-organized by China's leading virtual reality company Dapeng VR
I used 430 to write the driver for TLC5615, but why does 512 correspond to 5V, and isn't 5615 10 for DA?
If the timing is wrong, there will be no effect.