This circuit is a complete implementation of low-noise microwave fractional-N PLL, with adf4156 as the core fractional-N PLL device. Extend the PLL frequency range to 18 GHz using the adf5001 external prescaler. Using an ultra-low-noise op184 operational amplifier with appropriate biasing and filtering to drive the microwave VCO achieves a fully low-noise PLL at 12 GHz with measured integrated phase noise of 0.35 ps rms. This feature is typically used to generate the local oscillator frequency (LO) for applications such as microwave point-to-point systems, test and measurement equipment, automotive radar, and military applications.

Figure 1 shows the block diagram of the circuit. Synergy Microwave's 12 GHz VCO DXO11751220-5 was chosen for this circuit , although any VCO in the 4 GHz to 18 GHz range can be used as long as the loop filter is appropriately redesigned. Like most microwave VCOs, the Synergy VCO has a wide input tuning range of 0.5 V to 15 V, which requires an active PLL loop filter between the low-voltage ADF4156 charge pump (maximum output of 5.5 V) and the VCO input. The OP184 was chosen as the op amp for this active loop filter due to its good noise performance and rail-to-rail input/output. The op amp output noise will be fed through to the RF output and shaped by the active filter response, so the noise is low. Rail-to-rail input operation is also an important consideration for PLL active filters because a single op amp supply can be used. This is because the charge pump output (CPOUT) will start up at 0 V on power-up, which can cause problems for op amps that do not have a rail-to-rail input voltage range. This also allows the op amp's non-inverting input to be biased above ground with built-in headroom for any bias voltage changes caused by resistor mismatch or temperature changes. It is recommended to set the bias level to approximately half the charge pump supply (VP) to meet the input voltage range requirements with sufficient margin and to obtain the best charge pump spurious performance. This circuit note was measured with VP = 5 V and op amp common mode bias voltage = 2.2 V. To minimize reference noise feedthrough, place a large 1µF decoupling capacitor near the non-inverting op amp input pin, as shown in Figure 1. This capacitor and the 47 kΩ resistor form an RC filter with a cutoff frequency below 10 Hz.

Loop filter design

PLL loop filter design using ADI's free simulation tool ADIsimPLL www.analog.com/CN0174_ADIsimPLL .

This circuit chooses the inverting topology of pre-filtering. Pre-filtering is recommended to avoid overdriving the amplifier with very short current pulses from the charge pump, which may limit the slew rate of the input voltage. When using an inverting topology, you must ensure that the PLL IC allows the PFD polarity to be reversed, thus canceling out the op amp's inversion to drive the VCO with the correct polarity. The ADF4156 PLL has this PD polarity option.

Setup and measurements

Table 1 shows the settings for this circuit, and Figure 2 shows a comparison of the measured results and the predicted simulation performance of ADIsimPLL, which shows a good agreement. The measured integrated phase noise is 0.35 ps rms. The measurement setup is shown in Figure 3.

The performance of this or any high-speed circuit is highly dependent on proper PCB layout, including but not limited to power supply bypassing, controlled impedance lines (if required), component placement, signal routing, and power and ground planes. (For more information on PCB layout, see the MT-031 Tutorial , the MT-101 Tutorial , and the Practical Guide to High-Speed ​​Printed Circuit Board Layout articles.)