The PLL circuit shown in Figure 1 uses a 13 GHz fractional-N frequency synthesizer, a wideband active loop filter and a VCO. The 200 MHz frequency hopping phase within 5° has a phase establishment time of less than 5 μs.

This performance is achieved using an active loop filter with a bandwidth of 2.4 MHz. This wide-bandwidth loop filter performance is achieved because the ADF4159 phase frequency detector (PFD) has a maximum frequency of 110 MHz and the AD8065 op amp has a high gain-bandwidth product of 145 MHz.

The AD8065 op amp used in the active filter is capable of operating from a 24 V supply voltage, allowing control of most wideband VCOs with tuning voltages from 0 V to 18 V.

In PLL and VCO frequency synthesis systems, achieving frequency and phase settling times below 5 μs requires extremely wide loop bandwidth. Loop bandwidth (LBW) defines the speed of the control loop. A wider LBW allows faster settling time, but at the expense of phase noise and spurious signal attenuation.

The circuit shown in Figure 1 locks the ADF4159 to the RF _OUT /2 signal (~6 GHz) of a 12 GHz VCO (MACOM MAOC-009269). However, a VCO with an RF _OUT /2 signal up to 24 GHz can be used with the ADF4159 because it supports a maximum RF input of 13 GHz.

ADF4159 Fractional-N Frequency Synthesizer

In a fractional-N PLL, the noise from the sigma-delta modulator (SDM) peaks at half the PFD frequency (f _PFD ). For example, if the PFD frequency of a fractional-N PLL is 32 MHz, the unfiltered SDM noise peaks at 16 MHz. SDM noise destabilizes the loop, causing the PLL to fail to lock. Figure 2 shows the simulated phase noise curve under this condition.

The maximum PFD frequency of the ADF4159 is 110 MHz. This means that unfiltered SDM noise will peak at 55 MHz. Figure 3 shows the phase noise curve at a PFD frequency of 110 MHz. SDM noise occurs at large offsets from the carrier, so a loop filter can be used to filter it out.

The higher maximum PFD frequency of the ADF4159 is also important, as it is recommended to keep the LBW below 1/10 of the PFD frequency to ensure stability.

The maximum RF input frequency of the ADF4159 is 13 GHz. In this circuit configuration, the ADF4159 is actually driven by the VCO RF _OUT /2 signal. This means that when the VCO primarily outputs 12 GHz, the ADF4159 is actually locked at 6 GHz.

This configuration means that a 24 GHz VCO can be used, allowing a 12 GHz RF _OUT /2 signal to be fed back to the ADF4159. The evaluation board is sized to support a variety of 32-pin 5 mm × 5 mm LFCSP VCOs.

The supply voltage for the ADF4159's internal charge pump is 3.3 V. However, many wideband VCOs require tuning voltages up to 18 V. To meet this requirement, an active loop filter is used. The active filter multiplies the ADF4159's output tuning range by the op amp's gain. See the AD8065 section of this circuit note for more details.

The ADF4159 supports programmable charge pump current characteristics. This feature allows the user to easily modify the dynamic characteristics of the loop filter without changing the physical components. At this circuit's 2.5 mA charge pump current, the LBW is designed to be 2.4 MHz. The charge pump current can be reduced, thereby reducing the LBW without making physical changes to the loop filter components.

For ADIsimPLL simulation of this circuit, see the CN0302 Design Support Package ( http://www.analog.com/CN0302-DesignSupport ).

Active filter using AD8065

The AD8065 op amp has a supply voltage range of 24 V, a gain-bandwidth product (GBP) of approximately 145 MHz, and low noise (7 nV/√Hz). This property makes it ideal for active filters.

For most PLL applications, a phase margin of 45° to 55° is recommended to maintain a stable loop and minimize settling time. In an active loop filter (such as an op amp in the loop filter), additional poles will be generated at the op amp's unity gain frequency (or gain-bandwidth product). This extra pole introduces more phase lag, so loop instability may occur at different pole frequencies.

The higher the ratio of GBP to LBW, the lower the phase lag. For example, Table 1 shows that a GBP/LBW ratio of 10 will reduce the phase margin by 5.7°. If the GBP/LBW ratio is too low, the phase margin will also become very low, making the loop unstable.

This circuit uses a 2.4 MHz LBW, so the phase lag of the AD8065 145 MHz GBP is almost negligible (GBP/LBW = 60).

Comparison with OP184 active filter

The OP184 is an operational amplifier commonly used in active filter PLL applications. However, the OP184 is not suitable for extremely wide LBW applications because its GBP is 4 MHz. After optimizing the phase margin, the OP184 can be used in wide LBW applications, but the OP184 will eventually limit the maximum LBW.

The op amp in the active filter is configured in inverting mode, so the ADF4159 is programmed with the negative polarity of the phase detector. The inverting configuration is easier to implement because the op amp positive input can be biased at a fixed voltage that does not change as the op amp output changes, whereas in the non-inverting configuration the op amp output changes.

The AD8065 can also be used as a buffer to reduce the input capacitance of the VCO. For a 2.4 MHz LBW passive filter, the combined capacitance of the VCO input and the last capacitor of the filter must be approximately 1.5 pF. However, the VCO's measured input capacitance alone is 52 pF.

For loop filter capacitors, it is recommended to use C0G/NP0 ceramic capacitors (which have faster discharge times than standard capacitors) to minimize phase settling time.

This circuit requires excellent layout, grounding, and decoupling techniques as described in tutorials MT-031 and MT-101 . Complete schematics, layout files, and bill of materials can be found in the CN-0302 Design Support Package ( www.analog.com/CN0302-DesignSupport ).

Test Results

The measured phase noise of the circuit is shown in Figure 4. The frequency and phase settling time of 200 MHz frequency hopping are shown in Figure 5 and Figure 6 respectively.