The circuit in Figure 1 is a narrow-bandpass receiver front end based on the ADL5565 ultralow-noise differential amplifier driver and the AD9642 14-bit, 250 MSPS analog-to-digital converter (ADC).

Third-order Butterworth anti-aliasing filters are optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss caused by the filter network and other components is only 5.8 dB.

The overall circuit bandwidth is 18 MHz and the passband flatness is 3 dB. Using a 127MHz analog input, the measured signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) were 71.7dBFS and 92dBc respectively. The sampling frequency is 205 MSPS, so the IF input signal is positioned in the second Nyquist frequency region between 102.5 MHz and 205 MHz.

This circuit accepts a single-ended input and converts it to a differential signal using a wide bandwidth (3 GHz) Mini-Circuits TC2-1T 1:2 transformer. The 6 GHz differential amplifier ADL5565 has a differential input impedance of 200 Ω when operating at 6 dB gain and 100 Ω when operating at 12 dB gain. It also offers a 15.5 dB gain option.

The ADL5565 is an ideal driver for the AD9642, enabling a fully differential architecture in the ADC via bandpass filters, providing good high-frequency common-mode rejection while minimizing second-order distortion products. Depending on the input connection, the ADL5565 provides 6dB or 12dB of gain. This circuit uses a gain of 12dB to compensate for the insertion loss of the filter network and transformer (approximately 5.8dB), resulting in a total signal gain of 5.5dB.

An input signal of 1.5 dBm produces a 1.75 V pp full-scale differential signal at the ADC input.

The anti-aliasing filter is a third-order Butterworth filter designed using standard filter design procedures. The Butterworth filter was chosen for its passband flatness. The AC noise generated by the third-order filter has a bandwidth-to-noise ratio of 1.05 and can be designed with the help of a variety of free filter programs, such as Nuhertz Technologies Filter Free or Quite Universal Circuit Simulator (Qucs) Free Simulation.

For best performance, the ADL5565 should be loaded with a net differential load of 200 Ω. The 15Ω series resistor isolates the filter capacitor from the amplifier output, and the 100Ω resistor is in parallel with the downstream impedance, resulting in a net load impedance of 217Ω when a 30Ω series resistor is added.

A 5Ω resistor in series with the ADC input isolates internal switching transients from the filter and amplifier.

The 2.85kΩ input impedance is determined from a spreadsheet available for download on the AD9642 web page. Just use the parallel tracking mode value when the target IF frequency is at the center. The spreadsheet gives both real and imaginary values.

The third-order Butterworth filter is designed with a source impedance (differential) of 200Ω, a load impedance (differential) of 200Ω, a center frequency of 127MHz, and a 3dB bandwidth of 20 MHz. The values ​​calculated by a standard filter design program are shown in Figure 1. Since a larger series inductance is required, the 1.59 μH inductor is reduced to 620nH, and the 0.987pF capacitance is scaled up to 2.53 pF, thus leaving the 127 MHz resonant frequency unchanged and making the component values ​​more realistic.

The value of the second parallel capacitor is subtracted from the ADC's 2.5 pF internal capacitance, resulting in a value of 37.3 pF. In this circuit, the capacitor is placed near the ADC to reduce/absorb charge kickback.

The values ​​chosen for the final filter passive components (after adjusting for actual circuit parasitics) are shown in Figure 1. Table 1 summarizes the measured performance of the system with a 3 dB bandwidth of 18 MHz centered at 127 MHz. The total insertion loss of the network is approximately 5.8 dB. Figure 3 shows the frequency response; Figure 4 shows the SNR and SFDR performance.

Filter and interface design program

This section introduces common methods for amplifier/ADC and bandpass filter interface design. To achieve optimal performance (bandwidth, SNR, and SFDR), amplifiers and ADCs should impose certain design constraints on typical circuits.

1. The amplifier must refer to the correct DC loading recommended by the data sheet for optimal performance.
2. The correct number of series resistors must be used between the amplifier and filter loads. This is to prevent unwanted signal spikes within the passband.
3. The input to the ADC must be reduced with an external shunt resistor and the correct series resistor used to isolate the ADC from the filter. This series resistor will also reduce signal spikes.

The general circuit shown in Figure 5 is suitable for most high-speed differential amplifier/ADC interfaces and serves as the basis for a bandpass filter. This design approach tends to take advantage of the relatively high input impedance of most high-speed ADCs and the relatively low impedance of the driving source (amplifier) ​​to minimize the insertion loss of the filter.

The basic design process is as follows:

1. Set the external ADC termination resistor R _TADC so that the parallel combination with RA _ADC is between 200 Ω and 400 Ω.
2. _{Choose R KB} based on experience and/or ADC data sheet recommendations , typically between 5Ω and 36Ω.
3. Calculate the filter load impedance using
Z _AAFL = 2R _TADC ||(R _ADC + 2R _KB )

4. Select the amplifier external series resistor RR _A . If the amplifier differential output impedance is in the 100 Ω to 200 Ω range, RA _should be less than 10 Ω. If the amplifier output impedance is 12 Ω or less, RA should be between 5 Ω and 36 Ω.
5. Choose Z _{AAFL so that the total load Z AL} obtained by the amplifier is best suited for the specific differential amplifier selected by the following formula:
Z _AL = 2R _A + Z _AAFL
6. Calculate the filter source impedance using
Z _AAFS = Z _O + 2R _A

7. Use a filter design program or table, as well as source impedance Z _AAFS , load impedance Z _AAFL , filter type, bandwidth, and order to design the filter. The actual bandwidth used is 10% higher than the required bandwidth of the application's passband to ensure flatness over the frequency range.

After the above preliminary calculation, the following items of the circuit must be understood.

1. The C _AAF3 value must be at least 10 pF, several times greater than C _ADC . This minimizes the filter's sensitivity to _{CADC fluctuations.}
2. The ratio of Z _AAFL to Z _AAFS cannot be higher than about 7, which puts the filter within the limits of most filter tables and design programs.
3. C _AAF1 value must be at least 5 pF to minimize sensitivity to parasitic capacitance and component fluctuations.
4. The inductance L _AAF must be a reasonable value, at least a few nH.
5. C _AFF2 and L _AAF1 must be reasonable values. Sometimes circuit simulators make these values ​​too low or too high. To make these values ​​more reasonable, just keep the same resonant frequency and compare these values ​​to better standard value components.

In some cases, filter design programs can provide more than one unique solution, especially for higher order filters. Always choose the solution with the most reasonable combination of component values. Also choose a configuration that ends with the shunt capacitor so that the shunt capacitor combines with the ADC input capacitance.

Circuit Optimization Techniques and Tradeoffs

The parameters within this interface circuit are highly interactive; therefore optimizing all critical specifications of the circuit (bandwidth, bandwidth flatness, SNR, SFDR, and gain) is nearly impossible. However, by varying RA _and RKB _, the signal spikes that typically occur within the bandwidth response can be minimized.

_{The RA} value also affects SNR performance. Larger values ​​tend to slightly increase SNR while reducing bandwidth peaking because higher signal levels are required to drive the ADC full scale.

_{The R KB} series resistor at the ADC input is chosen to minimize distortion caused by any residual charge injection (from the internal sampling capacitance of the ADC). Increasing this resistance also tends to reduce signal spikes within the band.

However, increasing R _KB increases signal attenuation, so the amplifier must drive a larger signal to fill the ADC's input range.

To optimize the center frequency, the passband characteristics, series capacitance, and C _AAF2 can be changed within a small range.

The ADC's input termination resistor, _RTADC, is typically chosen so that the net ADC input impedance is between 200 Ω and 400 Ω, typical characteristic load values ​​for most amplifiers. Choosing a value that is too high or too low may adversely affect the linearity of the amplifier.

The trade-offs between the above factors can be somewhat difficult. In this design, each parameter is equally weighted; therefore, the values ​​selected represent the interface performance for all design features. In some designs, different values ​​may be chosen to optimize SFDR, SNR, or input drive levels, depending on system requirements.

The SFDR performance of this design depends on two factors: amplifier and ADC interface component values, as shown in Figure 1.

Note that the signal in this design is ac-coupled with a 0.1 μF capacitor to block the common-mode voltage between the amplifier, its termination resistor, and the ADC input. For more information on common-mode voltage, see the AD9642 data sheet.

Passive Components and PCB Parasitics Considerations

The performance of this or any high-speed circuit is highly dependent on proper printed circuit board (PCB) layout, including but not limited to power supply bypassing, controlled impedance traces (if required), component placement, signal routing, and power and ground planes . Details of high-speed ADC and amplifier PCB layout are provided in the guides MT-031 and MT-101 . Additionally, please refer to CN-0227 and CN-0238 .

For passive components within the filter, use low parasitic surface mount capacitors, inductors, and resistors. The inductor chosen is from the Coilcraft 0603CS series. The surface mount capacitor used in the filter is 5%, C0G, 0402 type to ensure stability and accuracy.

Complete documentation of the system is available in the CN-0279 Design Support Package