The circuit shown in Figure 1 is a 75 MHz low-power (25 mW total) direct digital synthesis (DDS) waveform generator. The output buffer and anti-image filter provide better spectral performance for frequency generation or clocking applications requiring sine, triangle, and square wave outputs up to 18 MHz.

Since low-power DDS devices are sampled data devices, they must be followed by appropriate anti-image filters to eliminate spectral images. However, the maximum current output is approximately 4 mA at the recommended 200 Ω load; therefore, an optimized low-power, low-distortion op amp buffer at the DDS output can provide low impedance for a high-quality 50 Ω filter driver source.

The combination of DDS, output buffer and seventh-order elliptical low-pass filter results in high-quality spectral performance.

The AD9834 is a 75 MHz complete low power (20 mW) DDS designed to provide true complementary current outputs up to 4 mA at output frequencies up to 37.5 MHz.

The AD8014 is a high-speed current feedback amplifier with a frequency of 400 MHz, a bandwidth of −3 dB, a slew rate of 4000 V/μs, and a settling time of 24 ns. The device features ultra-low voltage noise, current noise, and low distortion. Low power consumption (5.2 mW @ +4.5 V), low cost, and 30 mA current drive capability make the AD8014 an attractive buffer solution for the AD9834 output. The circuit operates at +3.3 V for the AD9834 and +4.5 V for the AD8014. DDS uses SPI interface. The circuit consists of three modules: DDS module, buffer module and low-pass filter module. Total circuit power consumption is approximately 25 mW.

DDS voltage output

The full-scale trim (FSADJUST) voltage and external resistor R _SET determine the magnitude of the full-scale DAC current. The nominal value of FSADJUST is 1.15 V and the typical value of the R _SET resistor is 6.8 kΩ.

The full-scale current of the AD9834 is as follows:

The circuit uses a nominal load of 200 Ω and a maximum full-scale current to achieve the desired voltage output without exceeding the DAC's compliance range.

There are two current outputs on board: IOUT and IOUTB. IOUT is unfiltered and IOUTB is filtered.

buffer amplifier

Due to the limited current and voltage compliance range of the DDS output, a buffer is required to provide higher current drive capabilities to the low-pass filter. Additionally, the buffer provides isolation between the DDS module and the filter module and converts the 200 Ω output impedance of the loaded DDS into the 50 Ω required to drive the terminating filter. In this circuit note, the low-power, high-performance current feedback op amp AD8014 is used as the output buffer of the AD9834. Its output drive current is greater than or equal to 30 mA. The feedback resistor in the AD8014 current feedback op amp sets the op amp's bandwidth. The AD8014 is a high-speed current feedback amplifier with a frequency of 400 MHz, a bandwidth of −3 dB, a slew rate of 4000 V/μs, and a settling time of 24 ns.

Figure 2 shows a 510 Ω feedback resistor. Since the op amp operates from a unipolar supply, the output needs to be centered around the midpoint of the supply voltage to prevent clipping. The voltage divider at point A provides a dc offset voltage of 2.25 V to the sinusoidal signal, resulting in an output swing of 2.25 V ± 0.3 V. For information on proper biasing of op amps in single-supply applications, see application note AN-581, "Biasing and Decoupling Op Amp in Single-Supply Applications . " For more information on current feedback amplifiers, see Tutorial MT-034, Current Feedback (CFB) Op Amp .

Seventh-order elliptical low-pass filter

Anti-image reconstruction must attenuate the inherent image frequency of the sampling system, as shown in Figure 1.

There are four basic filters that can be used as reconstruction filters: Kaul (elliptic), Chebyshev, Butterworth, and Bessel. Figure 3 shows the response curves of these four basic filters.

With the same order, the elliptical filter has a higher roll-off rate than the other three filters, making it a good choice for reconstruction filters. The filter used in this circuit note is a 7th order elliptical filter with a −3 dB bandwidth of 18 MHz.

Device selection

The resistors, capacitors and inductors used to implement the filter are all passive components and are affected by high frequencies. They must meet the following requirements:

• Low parasitic capacitance and inductance.
• Low tolerance value so that the measured response is close to the design response.
• Wide temperature range.
• Small size to minimize parasitic capacitance and inductance.

These are just some of the criteria to ensure that the measured filter response is close to the simulated filter response.

For more information on how to select passive components for a specific application, see Basic Linear Design: Chapter 10, "Passive Components . "

Filter design and performance

The seventh-order elliptical filter is shown in Figure 4, and the simulation and actual frequency response of the filter are shown in Figure 5. The software used is Advances Design System (ADS), version 2012.08. The actual filter components and manufacturers can be found in the bill of materials in the CN0304 Design Support package: http://www.analog.com/CN0304-DesignSupport .

The measured filter response was obtained using an Agilent E5061B network analyzer. The results show that the −3 dB bandwidth is 18 MHz. The passband attenuation is approximately 6 dB due to source and load termination.

In order to check the performance of the circuit, during the DDS performance test, the output frequency of the AD9834 was set to 15 MHz and the clock was 75 MSPS. The unfiltered output and filtered output are shown in Figure 6 and Figure 7 respectively.

As shown in Figure 7, the interfering images present in the unfiltered spectrum of Figure 6 are significantly reduced. The highest image spur at 60 MHz is suppressed by approximately 52 dB relative to the unfiltered output. This is equivalent to the measured attenuation of the filter at 60 MHz.

The filter attenuates the AD9834's 600 mV pp output by approximately 6 dB, and the sinusoidal x/x rolloff attenuates it by another 1 dB. Therefore, the output into a 50 Ω load is approximately 268 mV pp, or 94.7 mV rms. This is equivalent to 0.179 mW or −7.5 dBm.

For more information on DDS reconstruction filter design, see application note AN-837, DDS-based clock jitter performance versus DAC reconstruction filter performance .

This circuit must be built on a multilayer circuit board with a large area ground plane. For optimal performance, proper layout, grounding, and decoupling techniques must be used (refer to Tutorial MT-031, Grounding Data Converters and Solving the Mysteries of "AGND" and "DGND" and Tutorial MT-101, Go coupling technology ).

A complete design support package including schematics, board layout and bill of materials can be found at: http://www.analog.com/CN0304-DesignSupport .