The circuit shown in Figure 1 uses the ultra-low power, 18-bit 1 MSPS ADC AD7982 , driven by the low-power fully differential amplifier ADA4940-1 . A low-noise precision 5.0V reference ADR395 is used to provide the 5V power required by the ADC. All ICs shown in Figure 1 are available in small 3 mm × 3 mm LFCSP or 3 mm × 5 mm MSOP packages, helping to reduce board cost and space.
The ADA4940-1 in the circuit consumes less than 9 mW. The 18-bit 1 MSPS AD7982 ADC consumes only 7 mW (at 1 MSPS), which is much lower than similar ADCs on the market. This power consumption also varies with throughput. The ADR395 consumes only 0.7mW, bringing the total system power consumption to less than 17 mW.
Modern high-resolution SAR ADCs such as the AD7982 18-bit 1 MSPS PulSAR® ADC require differential drivers for optimal performance. In these applications, the ADC driver receives a differential or single-ended signal and performs the required level translation to drive the ADC input at the appropriate level.
Figure 1 shows the ADA4940-1 differential amplifier performing level translation and driving the 18-bit AD7982 differential input successive approximation PulSAR ADC. Using four resistors, the ADA4940-1 can either buffer the signal with a gain of 1 or amplify the signal for greater dynamic range. AC and DC performance are compatible with the 18-bit 1 MSPS PulSAR® ADC AD7982 and other 16- and 18-bit devices in the family, with sampling rates up to 2 MSPS. The circuit can also accept a single-ended input signal to produce the same fully differential output signal.
The AD7982 operates from a single VDD supply of 2.5 V. It has a built-in low-power, high-speed, 18-bit sampling ADC and a multi-function serial interface port. The reference voltage (REF) is obtained externally from the ADR395 precision low dropout (0.3 V) bandgap reference source and can be set independently of the supply voltage. The ADA4940-1 has DC-coupled inputs and outputs and optionally performs a differential or single-ended to differential conversion. It also buffers the drive signal. A single-pole 1.8 MHz RC (33 Ω, 2.7 nF) noise filter is placed between the op amp output and the ADC input. The filter also isolates the op amp output from switching surges caused by the internal sample-and-hold function at the ADC input.
The ADA4940-1 is powered by a 7 V supply (+6 V and –1 V), which allows the output to provide sufficient headroom for when the ADC full-scale input must swing between 0V and 5V.
Gain is set by the ratio of the feedback resistor (R2 = R4) to the gain resistor (R1 = R3). Additionally, this circuit can be used to perform single-ended or differential input to differential output conversion. If necessary, a terminating resistor can be connected in parallel to the input. Regardless of whether the input is single-ended or differential, the amplifier's input impedance can be calculated as shown in the MT-076 tutorial and the DiffAmpCalc™ Differential Amplifier Calculator ( www.analog.com/diffampcalc ).
If R1 = R2 = R3 = R4 = 1 kΩ, the single-ended input impedance is approximately 1.33 kΩ. The external 52.3 Ω termination resistor provides a 50 Ω source termination resistor. An additional 25.5 Ω at the inverting input (1025.5 Ω total) balances the parallel impedance of the 50 Ω source termination resistor driving the non-inverting input (52.3 Ω || 50 Ω = 25.5 Ω). However, if a differential source input is used, the differential input impedance is 2 kΩ. At this point, optionally terminate each input using two 52.3 Ω termination resistors.
For testing on this circuit, the signal generator produces a 10 V pp differential output. To reduce noise, the VOCM input is bypassed and set with an external 1% resistor for the widest output dynamic range with a 5V reference supply. With an output common-mode voltage of 2.5 V, each output of the ADA4940-1 swings between 0 V and 5 V and is out of phase, providing a differential signal with a gain of 1, 10 V pp to the ADC input. The FFT performance is shown in Figure 2 and summarized as follows:
INL and DNL performance are shown in Figure 3.
Blockdiagram
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