This circuit provides a high-performance, dual-channel IF sampling receiver; in base station terminology, it is also called a main receiver and a diversity receiver. This downconversion receiver uses a single IF frequency of 153.6 MHz and incorporates a dual-channel downconversion mixer, digitally controlled dual-channel VGA, dual-channel ADC, and clock synthesizer. This circuit accepts RF waveform input and outputs two 14-bit resolution digital data streams. It is optimized for high-frequency IF sampling, providing excellent spurious-free dynamic range (SFDR) performance of 79.61 dBc and a sampling rate of 122.88 MSPS at high gain settings.

This circuit includes an RF front-end and IF sampling receiver, consisting of a dual-channel balanced mixer, a wideband IF SAW filter, a digitally controlled dual-channel VGA and a dual-channel ADC. This circuit also has a built-in frequency synthesizer to generate the ADC sampling clock.

The ADL5356 dual-channel balanced mixer is designed to downconvert radio frequency (RF), primarily in the 1200 MHz to 2500 MHz range, to low intermediate frequencies (IF) in the 30 MHz to 450 MHz range.

The RF and LO input ports are AC coupled to prevent non-zero DC voltages from damaging the RF balun or LO input circuitry (part of the ADL5356). ADL5356 is configured in single-ended LO operating mode, and it is recommended that the LO drive is 0 dBm. The mixer's LOSW pin is connected to ground and only one of the two LO channels (LOI2) is used in this circuit.

The mixer differential IF interface requires a pull-up choke inductor to bias the open-collector output and set the output impedance match. The shunt impedance of the choke inductor used to couple the DC current into the IF amplifier should be chosen to provide the required output return loss. The real part of the mixer output impedance is approximately 200 Ω, which matches many commonly used SAW filters without the need for a transformer.

The receiver channel filtering is mainly completed by the 153.6 MHz, 20 MHz bandwidth Epcos B5206 SAW filter connected after the mixer. This filter has a typical insertion loss (IL) of approximately 9 dB and a matching characteristic impedance of 100 Ω differential. This SAW filter is matched to the mixer's 200 Ω differential output and AD8376 VGA 150 Ω differential input impedance through a simple LC reactive network .

Table 1 highlights the performance of a two-channel mixer plus SAW filter cascade. Please note that IP3 is the third-order intercept point, IP1dB is the input-referred −1 dB compression point, and NF is the noise figure.

The dual-channel, high-output linear VGA AD8376 is optimized for the ADC interface and provides 24 dB of receiver gain control. Two independent 5-bit binary codes change each attenuator setting in 1 dB steps, resulting in a gain setting range of +20 dB to −4 dB for each amplifier. The output third-order intercept point (IP3) and noise floor remain essentially unchanged over the available 24 dB gain range. This feature is important for variable gain receivers that need to maintain a constant instantaneous dynamic range as the receiver gain changes. The output IP3 of the AD8376 and subsequent antialiasing filter exceeds 50 dBm with a 2 V peak-to-peak composite signal.

The AD8376 provides a 150 Ω input impedance and is trimmed to drive a 150 Ω load impedance. The open-collector output structure requires DC biasing via an external bias network. Each channel output uses a set of 1 μH choke inductors to bias the open-collector output pins. The DGA output prior to analog-to-digital conversion is equipped with an optimized differential fourth-order bandpass anti-aliasing filter. Note that the anti-aliasing filter is terminated with shunt input and output resistors of approximately 300 Ω. The shunt resistor at the filter input is 309 Ω and the output is 330 Ω (consisting of two 165 Ω bias setting resistors), which together provide a nominal load impedance of 150 Ω to the AD8376.

The bandpass anti-aliasing filter is used to attenuate AD8376 output noise outside the Nyquist frequency region. Generally speaking, if an anti-aliasing filter of appropriate order is used, the SNR performance will be improved by several dB. The anti-aliasing filter consists of a fourth-order Butterworth filter and a resonant tank. The resonant tank eliminates the capacitive portion of the ADC load through resonance, helping to ensure that the ADC input looks like a true resistor at the target center frequency (see application notes AN-742 and AN-827). Additionally, AC coupling capacitors and bias chokes introduce more zeros into the transfer function. The overall frequency response exhibits a bandpass characteristic, which helps suppress noise outside the target Nyquist frequency region. The filter provides a 20 MHz passband centered at 153.6 MHz, flatness of 0.3 dB, and insertion loss of approximately 3 dB.

The ADC used is 14-bit AD9258 , whose sampling rate can reach up to 125 MSPS. The analog inputs of the AD9258 are driven by the AD8376 through a bandpass anti-aliasing filter. The ADC sampling rate is set to 122.88 MSPS and the full-scale input range is 2 V peak-to-peak. The AD9258 differential clock signal is provided by a clock generation IC AD9517-4 with an on-chip VCO. To achieve low jitter, use LVPECL level output OUT0. The AD9517-4 utilizes its internal VCO frequency of 1474.56 MHz to generate a 122.88 MHz output clock for the ADC. The loop filter designed using ADISimCLK™ simulation software provides a 60 kHz cutoff frequency and 50° phase margin, resulting in a timing jitter of approximately 160 fs rms. Assuming the input frequency is 153.6 MHz, use the formula SNR = 20 log(1/2π × f _IN × t _j ).

Using this circuit, excellent SFDR performance of 79.61 dBc (153.6 MHz) is achieved at maximum gain, as shown in Figure 2.