The circuit shown in Figure 1 is a complete linear variable differential transformer (LVDT) signal conditioning circuit that accurately measures linear position or linear displacement from a mechanical reference point. Synchronous demodulation in the analog domain is used to extract position information and suppress external noise. A 24-bit, sigma-delta analog-to-digital converter (ADC) digitizes position output information for high accuracy.

LV DT uses electromagnetic coupling between the active core and coil assembly. This non-contact (and therefore frictionless) working method is why they are widely used in aerospace, process control, robotics, nuclear, chemical plants, hydraulics, power turbines and other harsh working environments where long operating life and high reliability are required The main reason for sexual application.

The entire circuit including the LV DT excitation signal consumes only 10 mW. The circuit excitation frequency and output data rate are SPI programmable. The system allows trade-offs between programmable bandwidth and dynamic range, supporting bandwidths above 1 kHz with 100 dB dynamic range at 20 Hz bandwidth, making it ideal for precision industrial positioning and metrology applications.

The ADA2200 synchronous demodulator extracts position information by filtering the LVDT secondary signal before demodulating the signal to a low-frequency output voltage proportional to the LVDT core displacement. The ADA2200 drives the AD7192 24-bit Σ-Δ ADC, which digitizes and filters the output. The ADA2200 generates a synchronous LVDT excitation signal, and the ADG794 switch converts the CMOS level excitation signal into a precision 3.3 V square wave signal that drives the LVDT primary winding.

LVDT is an absolute displacement sensor that converts linear displacement into a proportional electrical signal. LVDTs are special wire-wound transformers with a movable core positioned to fit the location under test. The excitation signal is applied to the primary winding. As the core moves, the voltage on the secondary winding changes proportionally; from this voltage the position can be calculated.

There are many types of LVDTs, and the methods for extracting location information also vary. The circuit in Figure 1 uses a 4-wire mode LVDT. Subtraction is performed by connecting the secondary outputs of two LVDTs so that their voltages are opposite. When the LVDT core is at the zero position, the voltages on the two secondary terminals are equal and the voltage difference on the two windings is zero. As the core moves from the zero position, the voltage difference across the secondary winding increases. The LVDT output voltage phase changes depending on the direction.

The main clock of this circuit is generated by AD7192ADC. The ADA2200 accepts the master clock and generates all clocks within it, including the reference clock used as the LV DT excitation signal. The clock divider on the ADA2200 is configured to generate a 4.8 kHz excitation signal. The ADG794 converts the excitation signal into a precision ±3.3 V square wave signal. The +3.3 V is derived from the ADC supply voltage. The 3.3 V supply is also used as the ADC reference voltage; therefore, the ratio between the excitation signal and the ADC reference voltage can improve the noise performance and stability of the circuit. The system's 3.3 V supply is provided by the ADP151 low dropout regulator; the latter is driven from the 5 V supply.

The coupling circuit between the LVDT secondary winding and the ADA2200 input is used to limit the signal bandwidth and adjust the relative phase between RCLK and the ADA2200 input. The circuit is configured to have a maximum quadrature (phase = 90°) response and a minimum in-phase (phase = 0°) response. This allows the position to be determined just by measuring the quadrature output, making the ADA2200 output voltage less sensitive to changes in phase in the circuit. Temperature changes in the LVDT cause changes in the effective series resistance and inductance and are the main source of phase changes.

Anti-aliasing filters at the ADA2200 output maintain the signal bandwidth supported by the ADC. The output bandwidth of the AD7192's internal digital filter is approximately 0.27 times the output data rate. To maintain the output bandwidth at the 4.8 kHz maximum output data rate, the −3 dB corner frequency of the output antialiasing filter can be set to approximately 2 kHz. For systems requiring lower output data rates, the corner frequency of the antialiasing filter can be reduced accordingly.

Integrated synchronous demodulator

The ADA2200 integrated synchronous demodulator forms the core of the circuit. It uses unique charge sharing technology to perform discrete-time signal processing within the analog domain. The ADA2200 has a fully differential signal path. It consists of a high-impedance input buffer followed by a fixed low-pass filter (FIR decimation filter), a programmable IIR filter, a demodulator and a differential output buffer. Its input and output common-mode voltage is equal to 1.65 V (½ of the 3.3 V supply voltage).

The ADA2200 accepts the 4.92 MHz clock signal from the AD7192ADC and then generates all of its internal clocks, as well as the 4.8 kHz reference clock used as the LVDT excitation signal. The ADA2200 integrates a configurable clock divider that is programmable to support many different excitation frequencies.

CMOS switch

The ADG794 CMOS switch was chosen because of its low on-resistance, fast switching time, break-before-make switching action, and low cost.

The ADG794 converts the ADA2200's low-voltage CMOS level RCLK output into a low-impedance differential output square wave source that then drives an LVDT. To allow headroom for the switches to drive positive 3.3 V signals, the ADG794VDD input is powered from a 5 V supply.

LVDT

The circuit in Figure 1 can support a variety of LVDTs with only minor modifications. MeasurementSpecialties, Inc. E-100 LVDT is used in four-wire mode to demonstrate the main features of the circuit. The E-100 has a stroke range of ±2.54 mm, an output sensitivity of 240 mV/V at the stroke end, a maximum linearity error of ±0.5% in the full-scale range, and an operating frequency range of 100 Hz to 10 kHz. See the E-Series LVDT data sheet for complete details.

ADA2200 input coupling network

The ADA2200 input coupling network can be tuned to support different LVDTs. The LVDT secondary winding inductor and shunt capacitor (C4) form an oscillation circuit. The R4 and R33 resistors reduce the Q value of the oscillation circuit, making the circuit less susceptible to changes in the LVDT winding inductance and resistance, but the power consumption increases. The RC filter pair of R34/C24 and R35/C25 reduces the signal bandwidth while providing the additional degree of freedom needed to adjust the relative phase of the circuit. The maximum output of the ADA2200's internal phase-sensitive detector (PSD) occurs at 0° or 180° relative phase shift.

CN-0371Rev.0|Page3of6 Figure 2. User software screenshot Table 1. Relationship between noise performance and bandwidth ADC data rate (SPS) output bandwidth (Hz) ENOB (RMS) ENOB (PP) 4800130014.011.51200 325 14.9 12.4 300 80 15.8 13.3 75 20 16.2 13.6 13050-002 For the E-100 LVDT using a 4.8 kHz square wave excitation signal, the following component values ​​can be used to obtain the optimal phase at maximum output conditions:

• R4 = R33 = 2.2 kΩ
• R34 = R35 = 1 kΩ
• C24 = C25 = 3300 pF
• C4 = 0.01 μF

To tune this circuit, the phase can be measured by positioning the LVDT core to produce a near-full-scale output signal; then, the in-phase (I) and quadrature (Q) output signals are measured. Using these measurements the relative phase can be calculated:

Adjust the network components until the absolute value of θREL is less than approximately ±3°; this improves the sensitivity of the circuit to changes in the LVDT electrical parameters.

ADC selection and synchronization

The AD7192 Σ-Δ ADC was chosen because the device supports configurable output data rates and has a variety of different digital filter output options, allowing trade-offs between bandwidth and noise. The master clock output function allows easy locking of the ADC sampling clock frequency and the ADA2200 output signal. This is necessary to optimize digital filter performance. The value required to determine position from the LVDT signal is the average of one excitation clock cycle. Therefore, when the AD7192 output data rate is set to 4.8 kHz, which is one excitation clock cycle, the required average value is obtained. If the excitation clock period and ADC sampling frequency are not locked, the recovered position measurement information contains errors. Dividing by the output data rate effectively averages over multiple stimulus clock cycles.

The ADA2200 output signal contains electrical energy even when the LVDT core position is fixed, and the value is a multiple of the excitation signal frequency. Digital filter performance can also be analyzed in the frequency domain. The AD7192 has a sinc3 or sinc4 transfer function that zeroes out at multiples of the output data rate. These frequency components are the source of spurious errors. Output spurs can be suppressed by setting the ADC's output data rate to the excitation signal frequency (or a divisor of the excitation frequency). If the excitation clock period and ADC sampling frequency are not locked, the spurs will not fall at the zeros of the transfer function.

For complete circuit documentation including schematics, layout and bill of materials, see www.analog.com/CN0371-DesignSupport .

User software for performance analysis

The circuit supports a graphical user interface that makes it easy to configure devices on the board and evaluate circuit performance. The software has tabs that perform circuit calibration and device configuration, as well as display noise performance, linearity performance, and real-time position measurements. For a complete description of the software package, see the CN-0371 Software User Guide .

Noise analysis

The output noise of this circuit is a function of the ADC output data rate. Table 1 shows the effective number of bits (ENOB) of the digitized data relative to the ADC sampling rate, assuming a full-scale output voltage of 2.5 V. The noise performance of this circuit is independent of the LVDT core location.

If the ADA2200 output noise was frequency independent, the effective number of bits would be expected to increase by one every 4 folds down of the output data rate. The slower increase in ENOB at lower output data rates is caused by the 1/f noise of the output driver; this noise becomes the dominant component of the noise floor at lower output data rates.

Linearity test results

Linearity results are measured by first performing a two-point calibration at ±2.0 mm core displacement. From these two measurements, the slope and offset are determined, resulting in the desired straight line fit. Then, the core displacement is measured over a full scale range of ±2.5 mm. The linearity error is determined by subtracting the measured data from the expected straight line fit data.

The measured data shows that the circuit performance is better than the linearity performance specified in the E-Series LVDT data sheet.

Multiple LVDTs working simultaneously

Many applications use multiple LVDTs in close proximity. If these LVDTs operate at similar carrier frequencies, stray magnetic coupling may cause beat frequencies. The resulting beat frequency may affect measurement accuracy under these conditions. To avoid this situation, all LVDTs must work simultaneously.

Multiple ADA2200 devices can be synchronized by bringing the devices out of reset simultaneously. The ADA2200 exits reset mode on the first rising edge of CLKIN after the RST pin is deasserted. Therefore, driving all ADA2200 CLKIN pins and all RESETB lines from a single source is sufficient to ensure synchronous operation of the devices. Avoid deasserting RESETB near the rising edge of CLKIN to prevent the device from resetting on different clock edges. The RCLK output of the ADA2200 device can be monitored to ensure correct synchronization of the ADA2200 device.