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Sequence signal detector based on verilog

Overview

Sequence signal detector based on verilog, paper and source code. Design a sequence signal detector with specific requirements: when the input code stream is detected to be 10011110 or 11011010, the output detection signal is 1, otherwise it is 0, and the number of detected code streams is output at the same time (the maximum count value can not exceed 255, otherwise The count overflow signal is given as 1. When verification is required, the input code stream comes from the Sequence.txt file. Use the system function to read it in testbench and write the output information to the Outcome.txt file. The output information includes when and which code. flow, how many times it is detected).

Design Files

Sequence signal detector based on verilog

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