AG1280Q48 Minimum System Board V1

AG1280Q48 Minimum system

Version V1.0

• The shape and pin definition refer to Arduino Pro Mini, four-layer board
• Only a single 3.6V~5.5V power supply is needed, there are two LDOs on board, and the IO level is 3.3V
• Other onboard peripherals include: active crystal oscillator, SPI Nor Flash, buttons, programming interface, lights
• The SPI Flash power supply has a diode and can be programmed independently from the flying wires on the back.
• Mine was already ashes after I finished it.

AG1280Q48 Introduction

• It calls itself CPLD, but I think it is an FPGA with built-in Flash. .
• Logic Slice structure of LUT4+Carry+FF(chain)
• 1280 LUTs, 1 PLL, 14*4.5kbit Block RAM
• Cheap
• Downloaders are also cheap. You can use a USB Blaster from a certain store that costs more than a dozen yuan.

Tutorial 1: Use the built-in PLL to light up the onboard LED

This tutorial:

• Generates a less accurate clock by using the no-input mode of the built-in PLL
• Use this clock to light up the lights and randomly generate something on other IOs to prove that they are not broken.

1.1 Install software

This series of FPGA/CPLD requires Quartus II for logic synthesis and its own software Supra for Map, Place & Route, etc.

First install Quartus II 13.1 and the corresponding version of the Cyclone IV series device library.
Official website portal. Also, don’t download the latest version. I’ve been in a trap ()
As for the correct installation method of Quartus II, please search it yourself.

Then install AGM's software Supra, the download link can be found here on the official website .
While waiting for the Baidu Cloud download to end, you can do something else first.

1.2 Install software (Day 2)

Taking Windows system as an example, unzip the downloaded Supra compressed package to the appropriate location.
Supra does not require installation, just run bin/Supra.exe at startup.

1.3 Create a new project in Supra

Run Supra, select File - Project - New Project: Create a new project called blinky1280, fill in the project directory and project name as shown, and click Save.

1.4 Using the built-in PLL in Supra

Since we need to use the internal PLL, we need to create the IP first. The steps to create IP in Supra are as follows, select Tools - Create IP - Create PLL: Here we name the Verilog module generated by the IP inpll; select PLLX for PLL Type; write whatever you want for Input Frequency; select NO_REFERENCE for Feedback Mode; select 1 for output count ; Fill in the output frequency of Output 1 as 25MHz; click Generate: the actual and probably inaccurate frequency will be printed below. Then two files, inpll.ip and inpll.v, will be generated in the project directory. The former needs to be introduced in Supra during compilation, and the latter is the PLL module prototype that needs to be instantiated in the lighting code.

1.5 Establish Quartus II project and complete logic synthesis

Click Tools - Migrate and fill in the project details as shown in the figure: After clicking Next, run Quartus II and open the project (blinky1280.qpf in the directory). The project automatically includes a blinky1280.v.
Open the file and write the lighting code:

module blinky1280 (
    input wire clk,
    input wire rst_n,
    output wire led,
    output [17:0] gpio
);

    wire clk_pll_o;

    inpll pll_inst (
        .clkin(clk),        // PLL.clkin MUST connect to PIN_XX_GB
        .clkfb(clk_pll_o),
        .pllen(1'b1),
        .resetn(rst_n),
        .clkout0en(1'b1),
        .clkout1en(1'b0),
        .clkout2en(1'b0),
        .clkout3en(1'b0),
        .clkout0(clk_pll_o),
        .clkout1(),
        .clkout2(),
        .clkout3(),
        .lock()
    );

    reg [24:0] counter;

    assign led = counter[24];
    assign gpio[17:0] = counter[23:6];

    always @(posedge clk_pll_o or negedge rst_n) begin
        if (!rst_n) 
            counter <= 25'b0;
        else
            counter <= counter + 1;
    end

endmodule

Save the file. Then, make sure the PLL IP is set to Design Partition: select Tools - Tcl Scripts in Quartus II, select af_quartus.tcl in the directory and run:

1.6 Place & Route

When Quartus II completes logic synthesis, return to Supra and click Next: Do not click Finish here yet, first open blinky1280.asf in the project directory and assign pins:

set_location_assignment PIN_13 -to clk 
set_location_assignment PIN_48 -to led 
set_location_assignment PIN_41 -to rst_n 

set_location_assignment PIN_9 -to gpio[0]
set_location_assignment PIN_11 -to gpio[1]
set_location_assignment PIN_12 -to gpio[2]
set_location_assignment PIN_14 -to gpio[3]
set_location_assignment PIN_15 -to gpio[4]
set_location_assignment PIN_16 -to gpio[5]
set_location_assignment PIN_17 -to gpio[6]
set_location_assignment PIN_18 -to gpio[7]
set_location_assignment PIN_19 -to gpio[8]
set_location_assignment PIN_20 -to gpio[9]
set_location_assignment PIN_22 -to gpio[10]
set_location_assignment PIN_23 -to gpio[11]
set_location_assignment PIN_25 -to gpio[12]
set_location_assignment PIN_42 -to gpio[13]
set_location_assignment PIN_43 -to gpio[14]
set_location_assignment PIN_44 -to gpio[15]
set_location_assignment PIN_45 -to gpio[16]
set_location_assignment PIN_46 -to gpio[17]

Save and leave other parameters as default. Click Finish and Supra will start Place & Route. If everything goes well, the output will be like this: If it doesn't go well, try it yourself. If you can't solve the problem, it is recommended to switch back to Altera, or look forward to the original FAE coming from the sky.

1.7 Programming

Prepare a USB Blaster. I have tried the one from Taobao for more than a dozen yuan and the one from Zhengdian Atom, both of which can be used. The difference is that the cheaper one is slower.
First connect the USB Blaster to the board according to the pin definitions, then power on the board and connect the USB Blaster to the computer.
Open Tool - Program in Supra and click Query Device ID;
the Device ID of AG1280Q48 is 0x00120010. If connected correctly, this value will be read. Select the burning file just generated, where:

• blinky1280_sram.prg is programmed into the internal SRAM and is lost after power failure.
• If you need to save it after power off, select blinky1280_hybird.prg

Here we take SRAM as an example. After successful programming, as shown below, the light on the board should flash. Use an oscilloscope to measure other pins and you can see the square wave output:

Tutorial 2: Eating Ashes

Put the lit board in an anti-static bag from Lichuang Mall. The LDO bag used on this board is used here.
You also need to put the desiccant delivered every time the board is printed, and try to exhaust the air: then find a place to put it up. When eating ash, you need to pay attention to avoid external squeezing; avoid stepping on it after sliding; avoid accidentally eating; do not add eggs.

Additional information & references

The code and burning files involved in Tutorial 1 are in the attachment, which can be used to quickly test whether it is good or bad.

Other references: [LED light screen controller] Preliminary exploration of domestic FPGA AG10KSDE176 (1) - ReCclay The network disk link in this link contains Supra's user manual [LED light screen controller] AG10K burning program (2) - ReCclay AGM technology Collection of Questions and Answers-Haizhenyuan Technology (I didn’t ask for the full version of this