The 13th National Software and Information Technology Professionals Competition Individual Competition EDA Design and Development Subject Mock Test Questions
1- Mil is commonly used as the unit in circuit board design, and its conversion relationship with mm is ( ).
A. 1mil = 0.0254mm B. 1mil = 0.02mm C. 1mil = 0.254mm D. 1mil = 0.2mm
2-It is customary to divide printed circuit boards according to the number of layers on the board. Which of the following are not typical designs ( ).
A. Single-layer board B. Two-layer board C. Three-layer board D. Four-layer board
3-In PCB design, wiring layer switching is realized through ( ).
A. Silk screen B. Copper C. Solder mask D. Via
4-In the schematic design process, through which methods can the connection relationship between two components be established ( ).
A. Connected by wire
B. Place the same network label
C. Place text to explain
D. Modify to the same component number
5-In the circuit shown in the figure below, when Ui = 1V, Uo is ( ).
A. 0.1V B. 5.4V C. 0V D. -0.1V
6-A chip resistor, identified as 1002, the following description of the resistor is correct ( ).
A. The resistance value is 10K and the accuracy is 10%
B. The resistance value is 100K and the accuracy is 1%
C. The resistance value is 10K and the accuracy is 1%
D. The resistance value is 100K and the accuracy is 1O%.
7-When the voltage gain of the amplifier circuit is -20dB, its voltage amplification factor is ( ).
A. -20 times B. 20 times C. 10 times D. 0.1 times
8-After the printed circuit board design is completed, the process of rule checking is generally called ( ).
A. DRC B. RUL C. RCK D. PCB
9-A complete printed circuit board, mainly including ().
A. Insulating substrate B. Copper foil, holes C. Silk screen D. Solder mask
10-In circuit board design, the better design of ground loop is ( )
A. The loop area is large B. The loop area is small C. The loop area is vertical D. It has nothing to do with the loop area
Create a new component package and name it: BW-SOP-8. The package design requirements are shown in the figure below. (5 points)
Figure 1 Package design (BW-SOP-8)
Design requirements:
New Construction;
Open the schematic file sch.json provided in the "Resource Data Package"; complete the schematic design according to the following requirements.
1. According to the sample diagram given, complete the placement of component symbols, line drawing and network addition in the design area of the digital tube drive circuit (Design_Seg Driver). (12 points)
Figure 2 Digital tube drive circuit
Design requirements
2. In the operational amplifier design area (OPAMP Design), connect the power network, calculate the value of resistor R6 (voltage amplification factor is 1.5) according to the given circuit connection relationship, and fill in the calculation result in the name of the R6 component attribute . (8 points)
Schematic design description:
1. Preparation
Component number |
encapsulation |
B1 |
BAT-CR1220 |
C1,C5,C6,C7,C8,C9 |
C0805 |
C2,C4 |
CAP |
C3 |
C0805 |
CN1 |
USB-B |
D1 |
DIODE |
H1 |
HDR-F-2.54_1X3 |
LED1 |
LED0805 |
Q1 |
SOT-23-3 |
R1,R8,R19,R21,R22,R23,R24,R25,R26,R27 |
R0805 |
R2,R5,R16,R17,R18,R20,R28,R29,R30 |
R0805 |
R3,R4,R12,R14 |
R0805 |
R6 |
R0805 |
R7,R9 |
R0805 |
R10,R11,R13,R15 |
R0805 |
SEG1,SEG2 |
LED-SEG |
SP1 |
BUZZ |
SW1 |
SW-SMD_4P |
U2 |
SOP-16 |
U3 |
SOP-8 |
U4 |
SOP-8 |
U5,U7 |
SOP-16 |
U6 |
QFP-LQFP-44 |
U8 |
SOP-8 |
X1 |
XTAL-DT38 |
U1 |
SOIC-14_L8.7-W3.9-P1.27-LS6.0-BL |
Note: Package libraries other than "resource data package" cannot be used. 2. Component layout
Reasonably arrange the layout. Components should be arranged parallel or vertically to each other in order to be neat and beautiful. Overlapping of components is not allowed. The arrangement of components should be compact, and the components should be evenly distributed and dense throughout the entire layout.
3. Wiring design
Minimum line width: ≥14mil Line spacing: ≥6mil
Via size: 12mil/24mil Number of wiring layers: 2
Character layer: The top silk screen layer requires the characters to be placed neatly. Copper layer: top layer, bottom layer, GND network.
Closing rate: 100% 4. File export
Export the netlist from the schematic (Free PCB format) and rename it to USER.net.
1. According to the design requirements of the first library file of the test question, complete the design of the BW-SOP-8 package, export the Lichuang EDA package library file, and name it BW-SOP-8.json.
2. According to the schematic design requirements of question 2, complete the drawing of the schematic diagram, export the Lichuang EDA schematic diagram file, and name it SCH.json.
3. Complete the PCB design according to the PCB design requirements of question three, export the EDA PCB file, and name it PCB.json; export the netlist file (Free PCB format) to USER.net.
4. The compressed file package finally uploaded by the contestant should contain four files: BW-SOP-8.json, SCH.json, PCB.json, and USER.net.
5. Contestants who fail to name and submit documents as required will have their points deducted or be given zero points as appropriate. Contestants who submit documents that do not meet the test question requirements will have their points deducted or be given zero points as appropriate.
Video teaching materials: https://www.bilibili.com/video/BV1LP4y1E7Hd?p=7
Test question package: Please download it from the attachment.
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