1. The following are not component installation methods ( ).
A.Plug-in installation process B.Surface mounting
C. Liang's lead method D. Direct chip mounting
2. Among the following components, those that are passive components include ( ).
A.Resistance B.Capacitance
C.Inductor D.LED light
3. The basic process of generally designing PCB circuit boards is as follows:
Schematic design—[ ]—PCB layout—[ ]—[ ]—[ ]—PCB board manufacturing. ( )
① PCB wiring
② Design rule inspection and structural inspection
③PCB physical structure design
④ Wiring optimization and silk screen adjustment
A.①②③④ B.③①②④
C.①③④② D.③①④②
4. What kind of component packaging is DIODE commonly used for ( ).
A. Diode B. Capacitor
C.Inductor D.Transistor
5. DRC inspection can detect possible defects in electrical performance ( ).
A.Yes
B.Can't
6. Which of the following operations can be performed by administrators with member permissions of the EasyEDA project ( ).
A. Modify member permissions B. Delete project
C. Edit project D. Clone project
7. When a certain transistor is in amplification mode, the biases of its emitter junction and collector junction are ( ) respectively.
A. Forward bias, forward bias B. Forward bias, reverse bias C. Reverse bias, forward bias D. Reverse bias, reverse bias
8. In the TTL circuit, if the input terminal is left floating, its status will be ( ).
A. Equivalent to input high level B. Equivalent to input low level
C. Equivalent to grounding D. Uncertain status
9. The binary number (11010101) is converted into decimal number: , and converted into hexadecimal number is: .
10. Two signals of equal size and opposite polarity are added to the input end of the differential amplifier circuit, which are called: signals,
And adding two signals of equal size and polarity is called: signal.
Create a new component package and name it: LQ-QFN-24. The package design requirements are shown in the figure below. (5 points)
Figure 1 Package design (LQ-QFN-24)
Design requirements:
New Construction;
Open the schematic file sch.json provided in the "Resource Data Package"; complete the schematic design according to the following requirements.
1. According to the sample diagram given, complete the placement of component symbols, line drawing and network addition in the gyroscope circuit design area (Gyro Circuit). (12 points)
Figure 2 Gyroscope circuit
Design requirements
Figure 3 Relay circuit
Schematic design description:
1. Preparation
Component number |
encapsulation |
ASS_1/ASS_2 |
DC motor N20_horizontal assembly |
B1/B2 |
BAT-5AA_JX |
BUZZER1 |
BUZ-TH_BD12.0-P7.60-D0.6-FD |
C1-C5/C7-C20 |
C0603 |
C6 |
CAP-SMD_L3.2-W1.6 |
CN1/CN2 |
CONN-TH_5P-P1.50_ZH-5A |
D1 |
SOD-123FL_L2.6-W1.6-LS3.4-RD |
H1 |
HC-HR04 |
J1 |
HDR-M-2.54_1X4 |
J2 |
HDR-M-2.54_1X5 |
LDO1 |
SOT-89-3_L4.5-W2.5-P1.50-LS4.2-BR |
LDO2 |
SOT-23-5_L3.0-W1.7-P0.95-LS2.8-BR |
LED1 |
LED0603_RED |
LED2/LED3 |
LED0603_GREEN |
LED4/LED5 |
LED-TH-5MM_P2.54-L |
Q1 |
SOT-23_L2.9-W1.3-P1.90-LS2.4-BR |
Q2 |
SOT-23-3_L2.9-W1.6-P1.90-LS2.8-TR-CW |
R1-R22 |
R0603 |
RP1/RP2 |
10K chip adjustable resistor |
SW1 |
SW-TH_SK-12D02VG3 |
TP1-TP4 |
M3 copper pillar |
U1 |
SOT-23-5_L3.0-W1.7-P0.95-LS2.8-BR |
U2 |
LQ-QFN-24 |
U3 |
LQFP-48_L7.0-W7.0-P0.50-LS9.0-BL |
U4/U5 |
SOP-8_L4.9-W3.9-P1.27-LS6.0-BL |
U6 |
SOIC-8_L4.9-W3.9-P1.27-LS6.0-BL |
U7/U8 |
OPTO-TH_ITR9909 |
X1 |
OSC-SMD_L5.0-W3.2 |
Note: Package libraries other than "resource data package" cannot be used.
2. Component layout
Reasonably arrange the layout. Components should be arranged parallel or vertically to each other in order to be neat and beautiful. Overlapping of components is not allowed. The arrangement of components should be compact, and the components should be evenly distributed and dense throughout the entire layout.
3. Wiring design
Minimum line width: ≥12mil Line spacing: ≥6mil
Via size: 12mil/24mil Number of wiring layers: 2
Character layer: The top silk screen layer requires the characters to be placed neatly. Copper layer: top layer, bottom layer, GND network.
Cloth rate: 100%
1. Complete the design of the LQ-QFN-24 package according to the design requirements of the first library file of the test question, export the Lichuang EDA package library file, and name it LQ-QFN-24.json.
2. According to the schematic design requirements of question 2, complete the drawing of the schematic diagram, export the EasyEDA schematic diagram file, and name it SCH.json.
3. Complete the PCB design according to the PCB design requirements of question three, export the EDA PCB file, and name it PCB.json; export the netlist file (Free PCB format) to USER.net.
4. The file compression package finally uploaded by the contestant should contain four files: LQ-QFN-24.json, SCH.json, PCB.json, and USER.net.
5. Contestants who fail to name and submit documents as required will have their points deducted or be given zero points as appropriate. Contestants who submit documents that are not required by the test questions will have their points deducted or be given zero points as appropriate.
Video teaching materials: https://www.bilibili.com/video/BV1LP4y1E7Hd?p=12
Test question package: Please download it from the attachment.
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