74 chips to build 8bit ADC (analog-to-digital converter)

The ADC adopts successive approximation design, including:

   1. An 8bit R-2R DAC

   2. A TLV3501 high-speed RRIO voltage comparator

   3. A scanning signal generation unit

   4. An 8-bit controllable flip-flop register unit

   5. An 8-bit serial output management

   6. Oscillation and Clock Manager

   7. Simple sample holder

This module uses xdata memory mapping access similar to the 8051 microcontroller, and uses unsigned char xdata to allocate a fixed address through off-chip RAM equivalent address mapping.

Write an unsigned character into the ADC address to turn on the ADC.

The ADC automatically starts running. It first disconnects the keeper from the external signal, and then uses the principle of successive approximation to make the voltage value generated by the DAC closest to the input signal.

At this time, all 8 bits are scanned, the data is first stored in the 74374 output buffer register, and then the DAC is reset.

Finally, the ADC sends an interrupt signal to the microcontroller. The microcontroller uses the interrupt service function to read the 8-bit digital value from the off-chip RAM. The digital value enters the microcontroller through the P0 port of the 51 microcontroller.

Basic parameters:

       Power supply: 4.75-5.25V

       Input and output interface: CMOS level

       Maximum frequency: 1MHz

       Sampling rate: maximum 20Ksps

       Maximum retention time of the retainer: None (the retainer design failed and was abandoned)

       Valid analog input range: GND-VCC

       Limit analog input range: GND-3V~VCC+3V

       Input impedance: 500KΩ+

Physical map:

As a test, I wrote a simple program using the STC89C52RC microcontroller: timer 0 sends a start signal to the ADC every 1 second. After the ADC sampling is completed, external interrupt 0 is used to wake up the microcontroller to receive data, and then the data is displayed in 3-digit decimal format. LCD1602 screen with IIC interface. The source code is too simple, so it is not released.

The actual measurement results are as follows: testing a 1.5V single type III battery, the return value is 80

It is known that the ADC returns 255 at full scale and 0 at the lowest range, so the voltage is calculated:

The battery multimeter actually measured 1.498V, and the error was about 5%, which is barely acceptable.

At present, the design is still not perfect. Due to the use of OPA350+74HC4052 retainer, the leakage is very large and cannot be maintained at all;

The main frequency of 1MHz is very difficult for the switching speed of the voltage comparator.

The DAC output voltage is inaccurate, seriously affecting the measurement accuracy.

The original intention of this project is to teach ADC principles, so the design is very simple, please give me some QAQ

PCB preview:

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