DDS Arbitrary Waveform Generator

0.Directory

1. Project requirements
2. Implement function
3. Project Analysis
4. Procedure flow chart

1. Project requirements

(1) Through the high-speed DAC (10bits/125Msps) on the board and the logic of the DDS inside the FPGA, a waveform with adjustable waveform (sine wave, triangle wave, square wave), adjustable frequency (DC-), and adjustable amplitude is generated

(2) The frequency range of the generated analog signal is DC-20MHz, and the adjustment accuracy is 1Hz

(3) The amplitude of the generated analog signal is a maximum of 1Vpp, and the adjustment range is 0.1V-1V

(4) Display the current waveform shape, waveform frequency and amplitude on the OLED

(5) Use the on-board rotary encoder and buttons to switch waveforms and adjust parameters.

2. Implement functions

Use 2 buttons and 1 rotary encoder to set waveform parameters.

K1 controls waveform conversion, switching in the order of sine wave - triangle wave - square wave, and displayed through RGB indicators, corresponding to red, green and blue respectively.

K2 controls the amplitude, the amplitude range is from 0.1V-1Vpp, the default is 0.1Vpp, and it increases by 0.1Vpp each time it is pressed.

The rotary encoder controls the frequency. The maximum frequency range is 20MHz. After pressing the rotary encoder, the frequency step value can be adjusted. Each time the rotary encoder is pressed, the step value is x10.

(1) 0.5Vpp 1kHz sine wave

(2) 0.5Vpp 1kHz triangle wave

(3) 0.5Vpp 1kHz square wave

(4) 0.8Vpp 100kHz sine wave

(5) 1.0Vpp 1MHz sine wave

When the frequency reaches 10MHz, it cannot be observed due to the limited performance of the oscilloscope.

3. Implement ideas

It is mainly divided into input module, output module and display module.

3.1 Input module

The input module mainly contains key anti-shake and rotary encoder decoding IP cores, which integrate the input information and appropriately set the waveform, amplitude, frequency and frequency step.

3.1.1 Buttons

According to the above principle description, we can perform edge detection on the input pin of the button. When the input signal change is detected, the count is cleared and starts counting. When the count reaches 20ms, sampling is performed, and then the falling edge of each sampled value is performed. Detection, the detection result is output as a pulse for button debounce, and then the status output is flipped and output every time a falling edge is detected.

3.1.2 Rotary encoder

The rotary encoder gives two-phase square waves with a phase difference of 90 °, usually called A channel and B channel. One of the channels gives information related to the rotational speed. At the same time, the information on the direction of rotation is obtained through sequential comparison of the signals from the two channels.

3.2 Output module

The output module is divided into DAC driver and ROM (storage waveform data).

3.2.1 DAC

The DAC uses a high-speed DAC module based on 3Peaks' 3PD5651, which is simple to drive and requires only 10 data bits and clock signals.

Waveform data uses Guagle_wave software to generate mif format files, as shown in the figure below. Please note that you cannot use Save As when saving, otherwise an empty file will be saved. Just use File-Save.

3.2.2 ROM

ROM initialization can be completed through the ROM's IP core. In order to save space, the waveform is set to 256 bits. You can modify it yourself if necessary.

Use the phase accumulator to adjust the waveform frequency. For more detailed DDS tutorials, you can view dds_verilog [Electronic Forest] (eetree.cn) .

3.2.3 PLL

However, since the onboard crystal oscillator frequency is as low as 12M, using PLL for frequency multiplication can obtain a 200MHz clock as the clock signal of the DAC.

3.3 Display module

The display module uses a 0.96-inch monochrome OLED, which is very common. It is more cumbersome to use an FPGA driver. A state machine is used to write the initialization register and refresh the screen.

OLED has 6 wires, from left to right: GND, VCC, SCL, SDA, RES, DC, and uses 3.3V power supply. When using it, you can refer to the tutorial of Zhongjingyuan Electronics. According to the code when driving the microcontroller, write the registers for the OLED module. The number of different versions of the register commands during initialization varies. Use a lookup table to implement the memory, which can be optimized to call the official RAM or ROM. IP storage. In order to save space, the Chinese character library has been removed, and only the 5*8 dot matrix font data is retained. The uppercase letters or lowercase letters can also be deleted to further save space.

The OLED is divided into 4 lines, which display waveform, amplitude, frequency and frequency step respectively.

For a more detailed tutorial, see How to use FPGA to drive an OLED screen? (qq.com) .

4. Program flow

The RTL diagram is shown below.

The input module is WaveControl, the output module is DAC, and the display module is OLED12864.

The FreqStep part above sets the frequency step LED lights.

5. Resource occupation

The resource usage report is shown in the figure below: