Versatile 2.9V to 18V Interleaved Synchronous PWM Buck Controller

Overview

The ADP1829 is a versatile, dual-output, interleaved synchronous PWM step-down controller that generates two independent outputs over an input voltage range of 2.9 V to 18 V. Each channel can be configured to provide an output voltage from 0.6 V to 85% of the input voltage. The two channels are 180° out of phase, which reduces the current stress on the input capacitors and allows the use of smaller, lower cost input capacitors.

Design Files

The ADP1829 PWM buck controller uses an input voltage of 8.0 V to 16.0 V.pdf

All reference designs on this site are sourced from major semiconductor manufacturers or collected online for learning and research. The copyright belongs to the semiconductor manufacturer or the original author. If you believe that the reference design of this site infringes upon your relevant rights and interests, please send us a rights notice. As a neutral platform service provider, we will take measures to delete the relevant content in accordance with relevant laws after receiving the relevant notice from the rights holder. Please send relevant notifications to email: bbs_service@eeworld.com.cn.

It is your responsibility to test the circuit yourself and determine its suitability for you. EEWorld will not be liable for direct, indirect, special, incidental, consequential or punitive damages arising from any cause or anything connected to any reference design used.

Hot

Technical Resources More

Search Datasheet?

Supported by EEWorld Datasheet

Technical Videos More

Forum More

Update:2025-06-19 18:24:47

FPGA Design Practice (Logic)
FPGA Design Practice (Logic) is aimed at the vast number of FPGA/CPLD beginners. It explains FPGA/CPLD and related basic knowledge from scratch, and uses a motherboard-based learning kit that supports
SIMterix-Simplies~4~ Verilog
In the case of mixed integer and analog systems, simulation can only simulate Verilog or analog. If the digital part has only output, it is OK, just edit the voltage source and import the waveform fil
CCS Error
DEBUG: Error 2863: The control PushButton2 on dialog Installation_Type_Dialog needs the icon TypicalInstall.bmp in size 48x48, but that size is not available. Loading the first available sizeInternal
When the CEdit control is deleted by pressing the back key under EVC4.0\wince5, the content of CEdit is not updated
The cursor has moved over, but the string is still displayed there. It is updated only when the line is deleted. If you enter again, it will overlap with the previous word. And this problem only occur
After IAR compiles and downloads the code, how do I know the total length of the code and where the address is from and to?
Is there any automatically generated file that I can look at directly?Thanks!
Is it possible to add a count loop in the combinational logic of a three-stage state machine?
Assuming the clock cycle is 40ns, the state changes of my sequential circuit are about 80ns, 160ns, 160ns, 40ns. In a state, it relies on counting loops to stay in this state until the loop count meet

Datasheet More

Circuits More