FOC Solution Validation Version (DRV8353F)

I. Chip Overview

• 9V to 100V Three-Half-Bridge Gate Driver – Optional three low-side current shunt amplifiers • Functionally Safe and Quality-Managed – Documentation available to assist in IEC 61800-5-2 functional safety system design • Intelligent Gate Drive Architecture – Adjustable slew rate control for optimized EMI performance – VGS handshake and minimum dead-time insertion to prevent breakdown – 50mA to 1A peak pull-up current – ​​100mA to 2A peak sink current – ​​Reduced dV/dt through strong pull-down capability • Integrated Gate Driver Power Supply – High-side multiplier charge pump for 100% PWM duty cycle control – Low-side linear regulator • Integrated Three Current Shunt Amplifiers – Adjustable gain (5, 10, 20, 40 V/V) – Bidirectional or unidirectional support • 6x, 3x, 1x and independent PWM modes – Supports 120° sensor operation • Provides SPI or hardware interface • Low-power sleep mode (20µA at VVM = 48V) • Integrated protection features – VM undervoltage lockout (UVLO) – Gate drive power supply undervoltage (GDUV) – MOSFET VDS overcurrent protection (OCP) – MOSFET breakdown protection – Gate driver failure (GDF) – Thermal warning and thermal shutdown (OTW/OTSD) – Fault status indicator (nFAULT)

II. Project Introduction
1. Project status:
To be verified
2. Instructions for use
Required inputs:

FOC enable signal *1 (H4, shorted to 3V3, or a lump of solder)
I2S *1 (H1)
PWM with dead-time control *3 (dead-time control is optional)

Chip output:

Current sampling output *3 (H3)

 
Upper and lower board connection components:



Round head screws with washers M4 *5
4


Round head screws with washers M6 *8
5


Washers M4 *7 *0.5
8


Washers M6 *10 *0.5
10


Hex nuts M4
4.


Hexagonal nuts M6;
5.


Hexagonal iron posts M4*30+6;
4.


Hexagonal iron posts M6*30+8;
5.



3. Precautions:

Input voltage is recommended not to exceed 80V (maximum 90V);
motor rated current not to exceed 100A (5000W/3000WP); phase current 25A*3