[USB Network Adapter] USB 3.0 2.5G speed USB network adapter

 
Physical Product Images
Hardware Design
Interface Design

USB Interface: Utilizes a USB 3.0 interface to ensure sufficient bandwidth to support 2.5Gbps network transmission speeds. The interface design should be compatible with mainstream operating systems and USB standards.
Network Interface: An integrated transformer is selected to adapt to 2.5Gbps transmission speeds. The interface should support full-duplex communication and auto-negotiation.

Main Control Chip
1. The Realtek RTL8156B-CG/RTL8156BS-CG is a 10/100/1000M/2.5G Ethernet controller combined with a quad-speed IEEE 802.3 compliant media access controller (MAC), featuring a quad-speed Ethernet transceiver, USB 3.0 bus controller, and embedded memory, employing advanced digital signal processor technology and mixed-mode signal technology.
 
2. The RTL8156B-CG/RTL8156BS-CG provides high-speed wired network transmission via Category 5e UTP cable or Category 3 UTP (10Mbps only). Supports cross-detection and automatic correction, polarity correction, MDI switching, adaptive equalization, crosstalk cancellation, echo cancellation, timing recovery, and RF interference protection, providing robust transmission and reception capabilities through management, loopback diagnostics, and error correction.
3. The RTL8156B-CG features an embedded one-time programmable function (OTP) to replace external EEPROM memory (93C46/93C56/93C66), while the RTL8156BS-CG provides a built-in switching regulator.      
      
4. The RTL8156B-CG/RTL8156BS-CG utilizes USB 3.0, offering higher bandwidth and improved data protocols for exchange between host and device. USB 3.0 also provides advanced power management and energy-saving features.
5. The RTL8156B-CG complies with IEEE 802.3u specifications: IEEE 802.3ab specifications for 10/100Mbps Ethernet and 1000Mbps Ethernet, and IEEE 802.3bz 2500Mbps Ethernet specifications. Both support efficient power management. In addition to ACPI features, both support remote wake-up (including AMD Magic Packet and Microsoft Wake-up Framework), ACPI, and APM (Advanced Power Management) environments.              
6. The RTL8156B-CG/RTL8156BS-CG supports Microsoft Wake-up Packet Detection (WPD), providing wake-up frame information from the operating system, such as PatternID, OriginalPacketSize, SavedPacketSize, SavedPacketOffset, etc. WPD helps prevent accidental/unauthorized wake-ups of a sleeping computer.              
7. The RTL8156B-CG supports "RealWoW!". This feature allows the PC to reduce power consumption by maintaining a low-power sleep state. Note: The "RealWoW!" service needs to be registered upon first use.             
8. The RTL8156B-CG supports protocol offloading. It offloads some of the most common protocols to the NIC hardware to prevent spurious wake-ups and further reduce power consumption.
9. The RTL8156B-CG/RTL8156BS-CG can offload ARP (IPv4) and NS (IPv6) protocols in D3 power-saving mode.
The SOC module

references a 2.5G network card based on the RTL8156B chip using the USB 3.0 protocol – JLCPCB EDA open-source hardware platform (oshwhub.com), with the main chip design based on RTL8156+VL822+FE2.1 (fully verified) – JLCPCB EDA open-source hardware platform (oshwhub.com), and modifications have been made.

The USB interface module

uses a USB 3.0-A interface, requiring no external components. RX and TX can be directly connected to the SOC's TX and RX. (The SOC has a series capacitor.)

The network interface module

uses an independent transformer and an RJ45 port. Using an independent transformer is cheaper, although it increases the board design complexity compared to an integrated RJ45 and transformer design. (A separate transformer will be available later, with even lower costs).
The network port impedance is 90Ω differential, with a trace width of 9.3mil, a trace spacing of 5mil, and a ground plane spacing of 5mil. (The trace width may be slightly narrower depending on the actual routing.)

The PCB design

uses a two-layer board design, employing coplanar impedance ground planes for impedance control. (Actual measurements have not been taken; impedance cannot be controlled using free prototyping.)
The magnitude of the coplanar impedance is highly dependent on the trace width and ground plane spacing. The smaller the ground plane spacing and the wider the trace, the smaller the distributed capacitance and the higher the impedance.

The power supply design
 

uses one DC-DC converter and one LDO to provide the power required by the SOC.
The DC-DC converter uses an RT8096 with a 0.9V output. The output voltage calculation is 0.9 = 0.6(1 + 5/10). A 3.3uH inductor is used, but a 1uH inductor would be more suitable for 0.9V. A 10uH output capacitor is used according to the datasheet.
The LDO uses an RT9080-33GJ5 with a fixed output voltage of 3.3V; no other external components are required.

The exterior design

is currently unavailable; the casing is still under design. (Hoping to complete this with expert help, as I am not skilled in modeling). More data will be added

later . Expected Outcome: A stable and reliable USB 2.5G network card product that meets the needs of high-speed network transmission. Detailed hardware design documents and test reports for developers' reference and learning. An open hardware design platform and community support to promote innovation and development in network hardware technology.