Written test questions on digital circuits (summary)[Copy link]
Please list all the written test questions you have collected and discuss them. (1) The difference between synchronous circuits and asynchronous circuits Synchronous circuit: The clock input terminals of all flip-flops in the storage circuit are connected to the same clock pulse source, so the state changes of all flip-flops are synchronized with the applied clock pulse signal. Asynchronous circuit: The circuit does not have a unified clock. The clock input terminals of some flip-flops are connected to the clock pulse source. This means that the state changes of these flip-flops are synchronized with the clock pulse, while the state changes of other flip-flops are not synchronized with the clock pulse. (2) What is "wired AND" logic? To implement it, what are the specific requirements in terms of hardware characteristics? Connecting the output terminals of two gate circuits in parallel to realize the function of AND logic is called wired AND. In hardware, OC gates are used to implement it, and a pull-up resistor is added to the output port. (3) Explain setup and hold time violation, draw a diagram to illustrate, and explain the solution. Setup/hold time is the time requirement between the input signal and the clock signal of the test chip. Setup time refers to the time when the data is stable and unchanged before the rising edge of the trigger clock signal arrives. The input signal should arrive at the chip T time in advance of the rising edge of the clock (if the rising edge is valid). This T is the setup time. If the setup time is not met, the data cannot be entered into the trigger by this clock. Only at the next rising edge of the clock can the data be entered into the trigger. The hold time refers to the time that the data remains stable after the rising edge of the trigger clock signal arrives. If the hold time is not enough, the data cannot be entered into the trigger. Setup time (Setup Time) and hold time (Hold time). The setup time refers to the time that the data signal needs to remain unchanged before the clock edge. The hold time refers to the time that the data signal needs to remain unchanged after the clock jump edge. If the duration of the data signal before and after the clock edge trigger exceeds the setup and hold times, the excess is called the setup time margin and the hold time margin respectively.
(4) What are contention and hazard phenomena? How to judge? How to eliminate them? In combinational logic, contention is caused by the different delays in the input signal path of the gate, resulting in inconsistent arrival times at the gate. The generation of glitches is called hazard. If there are opposite signals in the Boolean expression, contention and hazard phenomena may occur. Solutions: One is to add elimination terms to the Boolean expression, and the other is to add capacitors outside the chip.
(5) Nouns: SRAM, SSRAM, SDRAM SRAM: static RAM. DRAM: dynamic RAM. SSRAM: Synchronous Static Random Access Memory. It is a type of SRAM. All accesses to SSRAM are initiated on the rising/falling edge of the clock. The address, data input and other control signals are all related to the clock signal. This is different from asynchronous SRAM, where access is independent of the clock, and data input and output are controlled by changes in the address. SDRAM: Synchronous DRAM Synchronous Dynamic Random Access Memory
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