Address decoding circuit

There are two methods of address decoding, one is a single decoding method, or called a word structure method; the other is a double decoding method, or called an XY decoding structure.

1) Single decoding method

The 16-word &TImes;4-bit memory has a total of 64 storage units, arranged in a matrix of 16 rows &TImes;4 columns. Each small square represents a storage unit. The circuit is equipped with 4 address lines, which can address 24 = 16 address logic units. If all 4 bits of each word are regarded as a logic unit, so that the 4 storage units of each logic unit have the same address code, The 16 word lines output by the decoding circuit can exactly select 16 logic units. Each time an address is selected, the 4-bit memory cells of the corresponding word line are selected at the same time. The selected memory cell will be connected to the data bit line, and the read or write operation can be implemented as required.

2)Double decoding structure

The 1-bit storage unit of each word constitutes a logical unit, and each small square in the figure represents a logical unit. The 16 addressable logic units are arranged into a 4&TImes;4 matrix. In order to reduce the number of outputs of the address decoding circuit, a dual decoding structure is adopted. The number of output lines for each address decoding is 22=4 (single decoding mode Requires 16 address output lines). In the figure, A0 and A1 are row address codes, and A2 and A3 are column address codes. The row and column addresses are decoded and output to four word lines X0~X3 and Y0~Y3 respectively. The X word line controls whether each row in the matrix is ​​connected to the bit line, and which logical unit in a row is selected is controlled by the Y word line. The selected unit will be connected to the data line to exchange information.

Address decoding circuit