Bluetooth wireless LAN transceiver chip RF2968 interface circuit design

RF2968 is a transceiver designed specifically for Bluetooth applications and operates in the 2.4GHz frequency band. Comply with Bluetooth radio specification version 1.1 power level two (+4dBm) or level three (0dBm) requirements. For power level 1 (+20dBm) applications, the RF2968 can be used with a power amplifier such as the RF2172. The chip contains circuits such as transmitter, receiver, VCO, clock, data bus, and chip control logic. Since the IF filter is integrated in the chip, RF2968 requires only a minimum of external components, avoiding external components such as IF SAW filters and symmetrical-asymmetric converters. The high-impedance state of the receiver input and transmit output eliminates the need for an external receiver/transmitter switch. RF2968 is connected to the antenna, RF bandpass filter, and baseband controller to achieve a complete Bluetooth solution. In addition to RF signal processing, RF3968 can also complete baseband control, DC compensation, data and clock recovery functions of data modulation.

Interface circuit principle: The RF2968 transmitter output is internally matched to 50Ω and requires an AC coupling capacitor. The receiver's low-noise amplifier input is internally matched to 50Ω impedance to the front-end filter. The receiver and transmitter connect a coupling capacitor between TXOUT and RXIN and share a front-end filter. In addition, the transmit channel can be amplified to +20dBm through an external amplifier, and the transmit gain control and receive signal strength indication of RF2968 can be turned on to make Bluetooth work at power level one. RSSI data is input through the serial port and provides 1dB resolution when exceeding the power range of -20 to 80dBm. The transmit gain control is modulated in 4dB steps and can be set via the serial port. The baseband data is sent to the transmitter via the BDATA1 pin. The BDATA1 pin is a bidirectional transmission pin, serving as an input in transmitting mode and as an output in receiving mode. The RF2968 implements Gaussian filtering of baseband data, FSK modulated IF current-controlled crystal oscillator (ICO), and IF upconversion to the RF channel frequency. The on-chip voltage controlled oscillator (VCO) generates a frequency that is half the local oscillator (LO) frequency, which is then multiplied to the exact LO frequency. The two external loop inductors between RESNTR+ and RESNTR- set the adjustment range of the VCO. The voltage is transmitted to the VCO from the on-chip regulator. The regulator is connected in the middle of the two loop inductors through a filter network. Due to the need for fast frequency hopping of Bluetooth, the loop filter (connected to DO and RSHUNT) is particularly important, as they determine the VCO's transition and setup time. Therefore, it is highly recommended to use the component values ​​provided in the circuit diagram. The RF2968 can use base clock frequencies of 10MHz, 11MHz, 12MHz, 13MHz or 20MHz and can support 2x the base clock at these frequencies. The clock can be sent directly to the OSC1 pin from the external reference clock through the DC blocking capacitor. If there is no external reference clock, a crystal oscillator and two capacitors can be used to form a reference oscillation circuit. Whether the reference frequency is externally or internally generated, use a resistor connected between OSC1 and OSC2 to provide the appropriate bias. The frequency tolerance of the reference frequency must be 20&TImes10-6 or better to ensure that the maximum allowable system frequency deviation remains within the demodulation bandwidth of the RF2968. The LPO pin uses a 3.2kHz or 32kHz low-power mode clock to provide a low-frequency clock to the baseband device in sleep mode. Taking into account the minimum sleep mode power consumption and flexible selection of the reference clock frequency, a 12MHz reference clock can be selected.

The receiver uses a low-IF architecture to minimize external components. The RF signal is down-converted to 1MHz, allowing the IF filter to be embedded into the chip. The demodulated data is output at the BDATA1 pin, and further data processing is completed using the baseband PLL data and clock recovery capacitor. D1 is the connection pin of the baseband PLL loop filter. Synchronous data and clock are output on the REDATA and RECCLK pins. If the baseband equipment uses RF2968 for clock recovery, the D1 loop filter can be omitted.